公开(公告)号：US20190155322A1

公开(公告)日：2019-05-23

申请号：US16259087

申请日：2019-01-28

Applicant: Allegro MicroSystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H03K19/003 ,  H01L43/02

Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

公开(公告)号：US10649481B2

公开(公告)日：2020-05-12

申请号：US16259087

申请日：2019-01-28

Applicant: Allegro MicroSystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

公开(公告)号：US10234887B2

公开(公告)日：2019-03-19

申请号：US15161529

申请日：2016-05-23

Applicant: Allegro Microsystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G06F3/02 ,  G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

公开(公告)号：US10056364B1

公开(公告)日：2018-08-21

申请号：US15481882

申请日：2017-04-07

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  Richard B. Cooper ,  Chung C. Kuo

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/40 ,  H01L29/866 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L29/402 ,  H01L29/866

Abstract: An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.

公开(公告)号：US20160282893A1

公开(公告)日：2016-09-29

申请号：US15161529

申请日：2016-05-23

Applicant: Allegro Microsystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H01L43/02

CPC classification number: G05F3/02 ,  H01L27/0259 ,  H01L27/0266 ,  H01L43/02 ,  H03K19/00361

Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

Abstract translation: 电子电路包括具有耦合到半导体衬底的第一掺杂型和参考端的半导体衬底。 在半导体衬底中形成具有第二掺杂类型的桶区。 具有第一掺杂类型的阱区形成在桶区内。 包括晶体管的驱动电路形成在阱区内并具有输出端。 控制电路耦合到驱动电路以控制驱动器电路。 第二晶体管在阱区内并且串联耦合在驱动器电路和输出端之间，第二晶体管具有耦合到驱动电路的第一端子和耦合到输出端的第二端子。 偏置电路耦合到第二晶体管的栅极端子并且被配置为将晶体管偏置为导通状态。

公开(公告)号：US09318481B1

公开(公告)日：2016-04-19

申请号：US14847519

申请日：2015-09-08

Applicant: Allegro Microsystems, LLC

Inventor： Zhixin Wang ,  Juin Jei Liou ,  Wei Liang ,  Richard B. Cooper ,  Maxim Klebanov ,  Harianto Wong

IPC: H01L29/66 ,  H01L27/02 ,  H01L29/868

CPC classification number: H01L27/0262 ,  H01L27/0255 ,  H01L29/66121 ,  H01L29/87

Abstract: In one aspect, a silicon-controller rectifier (SCR) includes a first N+ region; a first P+ region; a second N+ region; a second P+ region; and a P+/Intrinsic/N+ (PIN) diode disposed between the first P+ region and the second N+ region. The PIN diode includes a third N+ region, a third P+ region and an intrinsic material disposed between the third N+ region and the third P+ region. An anode terminal of the SCR connects to the first N+ region and the first P+ region and a cathode terminal of the SCR connects to the second N+ region and the second P+ region. A first distance between the third N+ region and the third P+ region controls the trigger voltage of the SCR and a second distance corresponding to a length of each of the third P+ region and the third N+ region controls the holding voltage of the SCR.

Abstract translation: 一方面，硅控制器整流器（SCR）包括第一N +区域; 第一个P +区; 第二个N +区; 第二个P +区; 和设置在第一P +区和第二N +区之间的P + /本征/ N +（PIN）二极管。 PIN二极管包括第三N +区，第三P +区和设置在第三N +区和第三P +区之间的本征材料。 SCR的阳极端子连接到第一N +区域，SCR的第一P +区域和阴极端子连接到第二N +区域和第二P +区域。 第三N +区域和第三P +区域之间的第一距离控制SCR的触发电压，并且对应于第三P +区域和第三N +区域中的每一个的长度的第二距离控制SCR的保持电压。