公开(公告)号：US20240005982A1

公开(公告)日：2024-01-04

申请号：US17852569

申请日：2022-06-29

申请人： Amlan Ghosh ,  John R. Riley ,  Feroze Merchant ,  Jaydeep Kulkarni

发明人： Amlan Ghosh ,  John R. Riley ,  Feroze Merchant ,  Jaydeep Kulkarni

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/11

CPC分类号： G11C11/412 ,  G11C11/419 ,  H01L27/1116 ,  H01L27/1104

摘要： A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.

公开(公告)号：US20170084316A1

公开(公告)日：2017-03-23

申请号：US14859884

申请日：2015-09-21

申请人： Jaydeep Kulkarni

发明人： Jaydeep Kulkarni

IPC分类号： G11C7/12 ,  G11C8/08 ,  G11C8/10

CPC分类号： G11C7/12 ,  G11C7/1048 ,  G11C8/08 ,  G11C8/10 ,  G11C17/12 ,  G11C2207/005

摘要： Some embodiments include apparatuses and methods having non-volatile memory cells, a data line associated with a group of non-volatile memory cells of the non-volatile memory cells, a first transistor coupled to the data line and a node, a second transistor coupled to the node and an additional node, a pull-up component coupled to the node and a supply node, and an additional pull-up component coupled to the additional node and the supply node.

公开(公告)号：US20170279348A1

公开(公告)日：2017-09-28

申请号：US15081445

申请日：2016-03-25

申请人： Jaydeep Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

发明人： Jaydeep Kulkarni ,  Yong Shim ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC分类号： H02M3/07 ,  H03K5/19 ,  H03K3/03

CPC分类号： H02M3/07 ,  H03K3/0315 ,  H03K5/19

摘要： Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.