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公开(公告)号：US07676625B2
公开(公告)日：2010-03-09
申请号：US11466734
申请日：2006-08-23
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.
摘要翻译： 多个PCIe交换机复合体被插入在多个I / O设备和多个微处理器复合体之间。 每个PCIe交换机包括多个PCIe交换机，其中每个交换机具有至少一个非透明端口。 非透明端口用于交叉耦合每个PCIe交换机，创建与每个I / O设备和每个微处理器相关联的HBA之间的路径的有源矩阵。 使用递归算法映射每个HBA（I / O设备）和每个微处理器之间的路径，为每个I / O设备提供对每个微处理器的直接存储器访问。
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2.发明申请DATA BUFFER ALLOCATION IN A NON-BLOCKING DATA SERVICES PLATFORM USING INPUT/OUTPUT SWITCHING FABRIC 有权使用输入/输出开关织物的非阻塞数据服务平台中的数据缓冲区分配公开(公告)号：US20080052432A1
公开(公告)日：2008-02-28
申请号：US11466726
申请日：2006-08-23
IPC分类号： G06F13/00
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.
摘要翻译： 通过远程缓冲区批量分配协议支持用于内存分配请求的微处理器复杂数据缓冲分配。 控制和数据放置的分离允许微处理器复杂负载共享的同时最大化，以及处理器间信令/元数据迁移的最小化。 分离处理控制与数据布局允许选择数据缓冲的位置，以便最大化总线带宽利用率并实现非阻塞交换行为。 这种分离减少了对处理器间通信和相关中断的需求，从而提高了计算效率和性能。
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公开(公告)号：US20080052443A1
公开(公告)日：2008-02-28
申请号：US11466734
申请日：2006-08-23
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A plurality of PCIe switch complexes are interposed between a plurality of I/O devices and a plurality of microprocessor complexes. Each PCIe switching complex comprises a plurality of PCIe switches wherein each switch possesses at least one non-transparent port. The non-transparent port is used to cross-couple each PCIe switch creating an active matrix of paths between the HBAs associated with each I/O device and each microprocessor. The paths between each HBA (I/O device) and each microprocessor are mapped using a recursive algorithm providing each I/O device with direct memory access to each microprocessor.
摘要翻译： 多个PCIe交换机复合体被插入在多个I / O设备和多个微处理器复合体之间。 每个PCIe交换机包括多个PCIe交换机，其中每个交换机具有至少一个非透明端口。 非透明端口用于交叉耦合每个PCIe交换机，创建与每个I / O设备和每个微处理器相关联的HBA之间的路径的有源矩阵。 使用递归算法映射每个HBA（I / O设备）和每个微处理器之间的路径，为每个I / O设备提供对每个微处理器的直接存储器访问。
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4.发明授权Data buffer allocation in a non-blocking data services platform using input/output switching fabric 有权数据缓冲区在使用输入/输出交换结构的非阻塞数据服务平台中进行分配公开(公告)号：US07594060B2
公开(公告)日：2009-09-22
申请号：US11466726
申请日：2006-08-23
IPC分类号： G06F13/00
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0656 , G06F3/0689
摘要： Data buffering allocation in a microprocessor complex for a request of memory allocation is supported through a remote buffer batch allocation protocol. The separation of control and data placement allows simultaneous maximization of microprocessor complex load sharing, and minimization of inter-processor signaling/metadata migration. Separating processing control from data placement allows the location of data buffering to be chosen so as to maximize bus bandwidth utilization and achieve non-blocking switch behavior. This separation reduces the need for inter-processor communication and associated interrupts thus improving computation efficiency and performance.
摘要翻译： 通过远程缓冲区批量分配协议支持用于内存分配请求的微处理器复杂数据缓冲分配。 控制和数据放置的分离允许微处理器复杂负载共享的同时最大化，以及处理器间信令/元数据迁移的最小化。 分离处理控制与数据布局允许选择数据缓冲的位置，以便最大化总线带宽利用率并实现非阻塞交换行为。 这种分离减少了对处理器间通信和相关中断的需求，从而提高了计算效率和性能。
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公开(公告)号：US20080052403A1
公开(公告)日：2008-02-28
申请号：US11466729
申请日：2006-08-23
CPC分类号： G06F11/2007 , G06F3/0601 , G06F2003/0692 , H04L49/1523 , H04L49/351 , H04L49/357 , H04L49/358
摘要： Dual ported Input/Output (“I/O”) routers couple I/O devices to a cross-coupled switching fabric providing multiple levels of data path redundancy. Each I/O router possesses two or more internal ports allowing each I/O router to access multiple switches in a cross-coupled switching fabric. The additional redundant paths between each I/O device and each microprocessor complex provide additional means to balance data traffic and thereby maximize bandwidth utilization. I/O routers can be interleaved with single HBAs establishing access a switching fabric that uses cross-coupled nontransparent ports thus providing each I/O device with multiple paths upon which to pass data. Data paths are identified by a recursive address scheme that uniquely identifies each data path option available to each I/O device.
摘要翻译： 双端口输入/输出（“I / O”）路由器将I / O设备耦合到交叉耦合交换结构，提供多级数据路径冗余。 每个I / O路由器拥有两个或多个内部端口，允许每个I / O路由器访问交叉耦合交换结构中的多个交换机。 每个I / O设备和每个微处理器复合体之间的附加冗余路径提供了额外的平衡数据流量的手段，从而最大化带宽利用率。 I / O路由器可以与单个HBA交织，建立访问交换结构，该交换结构使用交叉耦合的非透明端口，从而为每个I / O设备提供传递数据的多个路径。 数据路径由唯一标识每个I / O设备可用的每个数据路径选项的递归地址方案来标识。
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公开(公告)号：US5799175A
公开(公告)日：1998-08-25
申请号：US674316
申请日：1996-07-01
CPC分类号： G06F5/10
摘要： An information transfer system transfers information, in the form of at least one digital data word, from an source operating in a first clock signal domain defined by a first clock signal, to a destination operating in a second clock signal domain defined by a second clock signal. The information transfer system includes a buffer, a buffer storage element, a buffer retrieval element and a synchronizer. The buffer storage element stores the data word in the buffer under control of a data word present indication, and the buffer retrieval element retrieves the data word from the buffer under control of the second clock signal and a synchronized data word present indication. The synchronizer generates the synchronized data word present indication in response to the first clock signal, the second clock signal, and the data word present indication, thereby to synchronize the data word present indication from the first clock signal domain into the second clock signal domain.
摘要翻译： 信息传送系统以至少一个数字数据字的形式从在由第一时钟信号定义的第一时钟信号域中操作的源传送到在由第二时钟定义的第二时钟信号域中操作的目的地 信号。 信息传送系统包括缓冲器，缓冲存储元件，缓冲器检索元件和同步器。 缓冲存储元件在数据字存在指示的控制下将数据字存储在缓冲器中，并且缓冲器检索元件在第二时钟信号的控制下从缓冲器中检索数据字和同步的数据字存在指示。 同步器响应于第一时钟信号，第二时钟信号和数据字存在指示产生同步的数据字存在指示，从而使来自第一时钟信号域的数据字存在指示同步到第二时钟信号域。
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公开(公告)号：US07039323B2
公开(公告)日：2006-05-02
申请号：US09929153
申请日：2001-08-13
CPC分类号： H04B10/506
摘要： An optical transmitter for transmitting a first output data signal and a second output data signal, the optical transmitter comprising: a phase-locked-loop, the phase-locked-loop operable to receive a reference clock signal; a clock-recovery circuit, the clock-recovery circuit coupled to the phase-locked-loop, the clock-recovery circuit operable to receive a first input data signal; a latch-decision circuit, the latch-decision circuit coupled to the clock-recovery circuit; a latch, the latch coupled to the latch-decision circuit, the latch operable to receive the first input data signal and the second input data signal; a first electro-optical converter, the first electro-optical converter coupled to the latch, the first electro-optical converter operable to transmit the first output data signal; and a second electro-optical converter, the second electro-optical converter coupled to the latch, the second electro-optical converter operable to transmit the second output data signal.
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公开(公告)号：US06952419B1
公开(公告)日：2005-10-04
申请号：US09697730
申请日：2000-10-25
IPC分类号： H04L12/56
CPC分类号： H04L45/22 , H04L45/28 , H04L49/552 , H04L49/557
摘要： Methods and components in an interconnect system for improving the performance of the system with respect to increasing bandwidth in a serial link, increasing the processing speed of a packet in a node, and improving the calibration of links in the system are described. In one aspect of the present invention, a method of encoding framing data in a packet such that less than the normal number of framing bits is required. For example, a flit, the data unit sent over a serial link in one clock cycle, can be 88 bits in length, and a packet can be made up of one, two, or four flits. If the packet is a one- flit packet, two framing bits are inserted into the packet. If the packet is two flits, four framing bits are inserted into the packet, and if it is a four-flit packet, eight framing bits are inserted. In this way, space in the packet for data is maximized and the total number of bits of the packet can be determined either after reading a first framing bit if the packet is one flit or after reading a second framing bit if the packet is two or four flits long.
摘要翻译： 描述了用于提高系统在串行链路中增加带宽的性能的系统中的方法和组件，增加了节点中分组的处理速度，以及改进了系统中链路的校准。 在本发明的一个方面，一种在分组中对成帧数据进行编码的方法，使得需要少于正常数量的成帧位。 例如，在一个时钟周期内通过串行链路发送的数据单元的长度可以是88位，并且分组可以由一个，两个或四个flits组成。 如果数据包是一个单向数据包，则将两个帧位插入到数据包中。 如果分组是两个，则四个成帧位被插入到分组中，并且如果是四分组，则插入八个成帧位。 以这种方式，用于数据的分组中的空间被最大化，并且如果分组是一个飞行，则可以在读取第一成帧位之后或者如果分组是两个之后或在读取第二成帧位之后确定分组的总位数， 四its长。
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9.发明授权Method for superimposing a sequence number in an error detection code in a data network 有权将序列号叠加在数据网络中的错误检测码中的方法公开(公告)号：US06931581B1
公开(公告)日：2005-08-16
申请号：US09697731
申请日：2000-10-25
CPC分类号： H04L1/0032 , H03M13/09 , H04L1/0041 , H04L1/0061
摘要： A system and method for superimposing a sequence number of a packet into the CRC segment of the packet thereby allowing more bandwidth in the payload portion of the packet for carrying data is described. Also described is a method of acquiring additional information on the type of error in a packet, e.g., data transmission errors or sequence errors, from analyzing a CRC error. For example, a reported CRC error can be the result of the receipt of a packet with a sequence number the receiver is not expecting (which is a normal occurrence on transmission links due to transmitters resending packets that a receiver has already accepted) or can result from a real error in the transmission of a packet. A first error code check (CRC) value is calculated for the payload segment of a data packet. A second CRC value is calculated for the sequence number of the data packet. The first CRC value and the second CRC value are combined thereby creating a third CRC value. The third CRC value is then combined with the payload segment of the data packet thereby creating a data packet that can be transmitted across the link.
摘要翻译： 描述了一种用于将分组的序列号叠加到分组的CRC分段中的系统和方法，从而允许用于携带数据的分组的有效载荷部分中的更多带宽。 还描述了从分析CRC错误中获取关于分组中的错误类型的附加信息（例如数据传输错误或序列错误）的方法。 例如，报告的CRC错误可以是接收到具有接收器不期望的序列号的分组的结果（由于发送机重发发送方已经接收的分组，传输链路上的正常发生）或可能导致 从传输数据包的真实错误。 为数据包的有效载荷段计算第一个错误代码检查（CRC）值。 针对数据包的序列号计算第二个CRC值。 组合第一CRC值和第二CRC值，从而产生第三CRC值。 然后将第三CRC值与数据分组的有效载荷段组合，从而创建可以跨越链路传输的数据分组。
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10.发明授权
公开(公告)号：US5978419A
公开(公告)日：1999-11-02
申请号：US881471
申请日：1997-06-24
摘要： An information transfer system includes a transmitter and a receiver for transferring information over a differential communication link. The transmitter circuit includes a plurality of gated driver circuits each associated with one of a plurality separate phases of a clock signal, all of the gated driver circuits having respective outputs connected to a differential driver. Each gated driver circuit receives at a respective input a respective one of a plurality of selected information signals and transmits it over the communication link in response to the associated clock signal phase. A plurality of information selectors, each associated one of the gated driver circuits, are connected to receive a plurality of information signals each from a respective one of a plurality of digital information sources and selectively couple one of the information signals to the associated gated driver circuit as the respective selected information signal during a clock signal phase ahead of the clock signal phase ahead of the clock signal phase with which the associated gated driver circuit is associated. The receiver circuit includes a differential receiver which generates a single-ended signal representative of digital data in response the differential signals transmitted over the wires comprising the differential communication link. The differential receiver has a plurality of inputs each for connection to one of the wires of the differential communication link. A termination resistor is connected between the differential receiver inputs, and a continuity test circuit applies a test voltage to one of the differential receiver inputs during a link test operation. The digital receiver generates the single ended signal representative of digital data provided by the transmitter circuit the appropriate digital data value if the wires are continuous between the transmitter circuit and the receiver circuit. However, if at least one of the wires is not continuous, the differential receiver will provide a single-ended signal representative of the wrong digital data value.
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