Abstract:
Display driver circuitry loads data into display pixels. A regulator produces a power supply voltage for display driver circuitry that is measured by a monitor circuit. The monitor circuit asserts a mode selection signal in response to detection of a drop in power supply voltage during a power-down event. The display driver circuitry contains mode selection circuitry that is controlled by the mode selection signal. The mode selection circuit allows a controlled parallel driver shutdown sequence. During normal operation, the mode selection signal is deasserted and the display driver circuitry loads image data for the display into the display pixels. When the mode selection signal is asserted, mode selection circuitry and other circuitry in the display driver circuitry continue to operate during the power down so as to load safe data into the display pixels to avoid damaging the display when the display has been powered off.
Abstract:
A display may store extended display identification data for communicating the capabilities of the display to a source device such as a graphics processing unit. The extended display identification data may include a red primary color value, a green primary color value, and a blue primary color value. The primary color values in the extended display identification data may be determined during manufacturing. For example, a light sensor may measure the native primary colors of the display, and calibration computing equipment may determine if the native primary colors of the display are within a target color gamut. If the native primary colors of the display are outside of the target color gamut by an amount larger than a threshold, the primary color values in the extended display identification data may be adjusted to account for the color variation.
Abstract:
The embodiments discussed herein relate to systems, methods, and apparatus for synchronizing a pulse width modulation (PWM) dimming clock signal with a frame rate signal, line sync signal, and/or a horizontal sync signal of a display device. The PWM dimming clock signal can be generated by a synchronization block having a programmable offset/delay. The programmable offset/delay can control the offset or phase difference between an input and an output clock signal of the synchronization block. Depending on the clock rate of PWM dimming and/or panel resolution, the phase/offset delay can be adjusted to achieve the optimum front of screen performance. Additionally, an input clock generator/missing pulse detection block can output a programmed clock signal to the synchronization block in case of a missing external clock, or insert a pulse when there is a missing pulse detected.
Abstract:
A display may store extended display identification data for communicating the capabilities of the display to a source device such as a graphics processing unit. The extended display identification data may include a red primary color value, a green primary color value, and a blue primary color value. The primary color values in the extended display identification data may be determined during manufacturing. For example, a light sensor may measure the native primary colors of the display, and calibration computing equipment may determine if the native primary colors of the display are within a target color gamut. If the native primary colors of the display are outside of the target color gamut by an amount larger than a threshold, the primary color values in the extended display identification data may be adjusted to account for the color variation.