公开(公告)号：US11893413B2

公开(公告)日：2024-02-06

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5016 ,  G06F9/5022

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US11210100B2

公开(公告)日：2021-12-28

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US10922232B1

公开(公告)日：2021-02-16

申请号：US16400847

申请日：2019-05-01

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  David E. Kroesche ,  David J. Williamson

IPC: G06F12/08 ,  G06F12/0873 ,  G06F12/084 ,  G06F12/0888 ,  G06F12/0837

Abstract: An apparatus includes a control circuit and a cache memory with a plurality of regions. The control circuit receives a first and a second access request to access the cache memory. In response to determining that the first access request is from a particular processor core, and that the first access request is associated with a particular cache line in the cache memory, the control circuit stores the first access request in a cache access queue. In response to a determination that the second access request is received from a functional circuit, and that the second access request is associated with a range of a memory address space mapped to a subset of the plurality of regions, the control circuit stores the second access request in a memory access queue. The control circuit arbitrates access to the cache memory circuit between the first access request and the second access request.

公开(公告)号：US10445091B1

公开(公告)日：2019-10-15

申请号：US15085243

申请日：2016-03-30

Applicant: Apple Inc.

Inventor： Brett S. Feero

IPC: G06F9/30 ,  G06F12/0875

Abstract: In an embodiment, an apparatus includes a first buffer, a second buffer, and a control circuit. The control circuit may be configured to receive a first plurality of instructions included in a program. The control circuit may also be configured to store each of the first plurality of instructions in an entry of a first number of entries in the first buffer, arranged in the first number of entries dependent upon a received order. The control circuit may be further configured to select a second plurality of instructions from the first buffer. The second plurality of instructions may be selected dependent upon a program order. The control circuit may be configured to store each of the second plurality of instructions in an entry of a second number of entries in the second buffer, arranged in the second number of entries dependent upon the program order.

公开(公告)号：US20220137975A1

公开(公告)日：2022-05-05

申请号：US17527872

申请日：2021-11-16

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US20220083369A1

公开(公告)日：2022-03-17

申请号：US17143149

申请日：2021-01-06

Applicant: Apple Inc.

Inventor： Michael D. Snyder ,  Ronald P. Hall ,  Deepak Limaye ,  Brett S. Feero ,  Rohit K. Gupta

IPC: G06F9/46 ,  G06F9/50 ,  G06F9/54

Abstract: An embodiment of an apparatus includes a processing circuit and a system memory. The processing circuit may store a pending request in a buffer, the pending request corresponding to a transaction that includes a write request to the system memory. The processing circuit may also allocate an entry in a write table corresponding the transaction. After sending the transaction to the system memory to be processed, the pending request in the buffer may be removed in response to the allocation of the write entry.

公开(公告)号：US10776125B2

公开(公告)日：2020-09-15

申请号：US16210231

申请日：2018-12-05

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta

IPC: G06F9/38 ,  G06F12/0815 ,  G06F12/084

Abstract: In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

公开(公告)号：US20200218540A1

公开(公告)日：2020-07-09

申请号：US16242151

申请日：2019-01-08

Applicant: Apple Inc.

Inventor： Aditya Kesiraju ,  Brett S. Feero ,  Nikhil Gupta ,  Viney Gautam

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F9/52

Abstract: In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

公开(公告)号：US10203959B1

公开(公告)日：2019-02-12

申请号：US14993627

申请日：2016-01-12

Applicant: Apple Inc.

Inventor： Brett S. Feero

IPC: G06F9/30

Abstract: Techniques are disclosed relating to reducing power consumption of a branch prediction unit. In one embodiment, an integrated circuit includes an instruction fetch unit configured to fetch a set of instructions that includes a call instruction. The instruction fetch unit is further configured to determine whether the set of instructions includes a first type of branch instruction after the call instruction, and in response to determining that the set does not include the first type of branch instruction, to disable a first branch predictor circuit configured to predict an execution result of the first type of branch instruction. In various embodiments, the instruction fetch unit is configured to determine that the set of instructions includes a second type of branch instruction after the call instruction, and in response, enable a second branch predictor circuit configured to predict an execution result of the second type of branch instruction.

公开(公告)号：US20250094355A1

公开(公告)日：2025-03-20

申请号：US18544110

申请日：2023-12-18

Applicant: Apple Inc.

Inventor： Brett S. Feero ,  Brian T. Mokrzycki ,  Jonathan Y. Tong ,  Michael D. Snyder ,  James N. Hardage

IPC: G06F12/1027

Abstract: Techniques are disclosed relating to using an instruction (e.g., a pre-translate instruction) to lock translations in TLB entries. The execution of the instruction may include storing translation information in a TLB entry, and setting an indication that the entry is locked. The processor circuitry may receive an invalidate command corresponding to the locked entry. Processor circuitry may, in response to the invalidate command and based on the indication that the entry is locked, maintain the locked entry in a valid state in the translation lookaside buffer circuitry, notwithstanding the invalidate command. Processor circuitry may be further configured to modify previously-stored data in a given entry to aggregate, in the entry, translation information for multiple regions of the second address space.