Arbitration sub-queues for a memory circuit

    公开(公告)号:US12079144B1

    公开(公告)日:2024-09-03

    申请号:US18054280

    申请日:2022-11-10

    Applicant: Apple Inc.

    CPC classification number: G06F13/1642 G06F13/161 G06F13/1668 G06F13/374

    Abstract: An apparatus includes a communication bus circuit, a memory circuit, a queue manager circuit, and an arbitration circuit. The communication bus circuit includes a command bus and a data bus separate from the command bus. The queue manager circuit may be configured to receive a first memory request and a second memory request, each request including a respective address value to be sent via the command bus. The first memory request may include a corresponding data operand to be sent via the data bus. The queue manager circuit may also be configured to distribute the first memory request and the second memory request among a plurality of bus queues. Distribution of the first and second memory requests may be based on the respective address values. The arbitration circuit may be configured to select a particular memory request from a particular one of the plurality of bus queues.

    Communication Channels with both Shared and Independent Resources

    公开(公告)号:US20230064187A1

    公开(公告)日:2023-03-02

    申请号:US17455321

    申请日:2021-11-17

    Applicant: Apple Inc.

    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

    Communication channels with both shared and independent resources

    公开(公告)号:US11824795B2

    公开(公告)日:2023-11-21

    申请号:US17455321

    申请日:2021-11-17

    Applicant: Apple Inc.

    CPC classification number: H04L47/805 H04L47/25 H04L47/39

    Abstract: Techniques are disclosed relating to merging virtual communication channels in a portion of a computing system. In some embodiments, a communication fabric routes first and second classes of traffic with different quality-of-service parameters, using a first virtual channel for the first class and a second virtual channel for the second class. In some embodiments, a memory controller communicates, via the fabric, using a merged virtual channel configured to handle traffic from both the first virtual channel and the second virtual channel. In some embodiments, the system limits the rate at which an agent is allowed to transmit requests of the second class of traffic, but requests by the agent for the first class of traffic are not rate limited. Disclosed techniques may improve independence of virtual channels, relative to sharing the same channel in an entire system, without unduly increasing complexity.

    Temperature-based bandwidth compensation for memory traffic

    公开(公告)号:US12093541B1

    公开(公告)日:2024-09-17

    申请号:US17929925

    申请日:2022-09-06

    Applicant: Apple Inc.

    CPC classification number: G06F3/0631 G06F3/0611 G06F3/0659 G06F3/0679

    Abstract: Techniques are disclosed relating to bandwidth compensation for certain memory traffic at high temperatures. In some embodiments, processor circuitry is configured to execute memory access operations for multiple traffic classes, including a first traffic class (e.g., real-time traffic) associated with a bandwidth quality-of-service parameter and a second traffic class (e.g., low-latency traffic). In some embodiments, memory controller circuitry is configured to access storage circuitry to perform the memory access operations, determine a temperature value associated with the storage circuitry, and, based on detection of a first temperature scenario for the storage circuitry, allocate memory access operations among the first and second traffic class according to a first allocation policy. In some embodiments, in response to detection of a second temperature scenario for the storage circuitry, memory controller circuitry allocates memory access operations among both traffic classes according to a second allocation policy. The second allocation policy may provide greater bandwidth for the first class than the first allocation policy.

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