公开(公告)号：US20160071574A1

公开(公告)日：2016-03-10

申请号：US14482613

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Ramesh Arvapalli ,  Andrew L. Arengo

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C11/413

Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Abstract translation: 公开了用于SRAM的低延迟初始化的方法和各种电路实施例。 在一个实施例中，IC包括耦合到至少一个功能电路块的SRAM。 SRAM包括以行和列排列的多个存储位置。 功能电路块和SRAM可以在不同的电源域中。 在初始上电或恢复电源时，功能电路块可以断言初始化信号以开始初始化过程。 响应于初始化信号，电平移位器可以在与SRAM相关联的解码器中强制断言各种选择/使能信号。 此后，可以将初始化数据写入SRAM。 可以逐行地执行写入初始化数据，其中一行中的所有列被基本上同时写入。

公开(公告)号：US09455000B2

公开(公告)日：2016-09-27

申请号：US14624605

申请日：2015-02-18

Applicant: Apple Inc.

Inventor： Ramesh Arvapalli ,  Greg M. Hess

IPC: G11C7/06 ,  G11C8/10

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C8/10 ,  G11C8/12

Abstract: A first plurality of storage cells may be coupled to a first pair of data lines, and a second plurality of storage cells may be coupled to a second pair of data lines. Each storage cell in the first plurality of storage cells may be configured to generate a first output signal on the first pair of data lines in response to an assertion of a respective one of first plurality of selection signals, and each storage cell in the second plurality of storage cells may be configured to generate a second output signal on the second pair of data lines in response to the assertion of a respective one of a second plurality of selection signals. Circuitry may assert a given selection signal from either the first or second plurality of selection signals. An amplifier circuit may amplify either the first or second output signal.

Abstract translation: 第一多个存储单元可以耦合到第一对数据线，并且第二多个存储单元可以耦合到第二对数据线。 第一多个存储单元中的每个存储单元可以被配置为响应于第一多个选择信号中的相应一个选择信号的断言而在第一对数据线上产生第一输出信号，并且第二多个存储单元中的每个存储单元 存储单元可以被配置为响应于第二多个选择信号中的相应一个的断言而在第二对数据线上产生第二输出信号。 电路可以从第一或第二多个选择信号中断一个给定的选择信号。 放大器电路可以放大第一或第二输出信号。

公开(公告)号：US20160240231A1

公开(公告)日：2016-08-18

申请号：US14624605

申请日：2015-02-18

Applicant: Apple Inc.

Inventor： Ramesh Arvapalli ,  Greg M. Hess

IPC: G11C7/06 ,  G11C8/10

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C8/10 ,  G11C8/12

Abstract: A first plurality of storage cells may be coupled to a first pair of data lines, and a second plurality of storage cells may be coupled to a second pair of data lines. Each storage cell in the first plurality of storage cells may be configured to generate a first output signal on the first pair of data lines in response to an assertion of a respective one of first plurality of selection signals, and each storage cell in the second plurality of storage cells may be configured to generate a second output signal on the second pair of data lines in response to the assertion of a respective one of a second plurality of selection signals. Circuitry may assert a given selection signal from either the first or second plurality of selection signals. An amplifier circuit may amplify either the first or second output signal.

Abstract translation: 第一多个存储单元可以耦合到第一对数据线，并且第二多个存储单元可以耦合到第二对数据线。 第一多个存储单元中的每个存储单元可以被配置为响应于第一多个选择信号中的相应一个选择信号的断言而在第一对数据线上产生第一输出信号，并且第二多个存储单元中的每个存储单元 存储单元可以被配置为响应于第二多个选择信号中的相应一个的断言而在第二对数据线上产生第二输出信号。 电路可以从第一或第二多个选择信号中断一个给定的选择信号。 放大器电路可以放大第一或第二输出信号。

公开(公告)号：US09286971B1

公开(公告)日：2016-03-15

申请号：US14482613

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Ramesh Arvapalli ,  Andrew L. Arengo

IPC: G11C11/00 ,  G11C7/00 ,  G11C8/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1078 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C11/413

Abstract: A method and various circuit embodiments for low latency initialization of an SRAM are disclosed. In one embodiment, an IC includes an SRAM coupled to at least one functional circuit block. The SRAM includes a number of storage location arranged in rows and columns. The functional circuit block and the SRAM may be in different power domains. Upon initially powering up or a restoration of power, the functional circuit block may assert an initialization signal to begin an initialization process. Responsive to the initialization signal, level shifters may force assertion of various select/enable signals in a decoder associated with the SRAM. Thereafter, initialization data may be written to the SRAM. Writing initialization data may be performed on a row-by-row basis, with all columns in a row being written to substantially simultaneously.

Abstract translation: 公开了用于SRAM的低延迟初始化的方法和各种电路实施例。 在一个实施例中，IC包括耦合到至少一个功能电路块的SRAM。 SRAM包括以行和列排列的多个存储位置。 功能电路块和SRAM可以在不同的电源域中。 在初始上电或恢复电源时，功能电路块可以断言初始化信号以开始初始化过程。 响应于初始化信号，电平移位器可以在与SRAM相关联的解码器中强制断言各种选择/使能信号。 此后，可以将初始化数据写入SRAM。 可以逐行地执行写入初始化数据，其中一行中的所有列被基本上同时写入。

公开(公告)号：US09236100B1

公开(公告)日：2016-01-12

申请号：US14497566

申请日：2014-09-26

Applicant: Apple Inc.

Inventor： Greg M. Hess ,  Ramesh Arvapalli

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1021 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/22 ,  G11C16/24 ,  G11C2207/2281

Abstract: An apparatus, system, and method are contemplated in which the apparatus may include a memory with a plurality of pages, circuitry, and a plurality of pre-charge circuits. The circuitry may be configured to receive a first read command and address, corresponding to a given page. The plurality of pre-charge circuits may be configured to charge a plurality of data lines to a predetermined voltage. The circuitry may be configured to read data values from the memory, and transfer the data values to the plurality of data lines. The plurality of pre-charge circuits may be configured to maintain the data on the plurality of data lines. The circuitry may select a first subset of the maintained data, receive a second read command and a second address by the memory, and select a second subset of the maintained data responsive to a determination that the second address corresponds to the given page.

Abstract translation: 设想一种装置，系统和方法，其中装置可以包括具有多页，电路和多个预充电电路的存储器。 电路可以被配置为接收对应于给定页面的第一读取命令和地址。 多个预充电电路可以被配置为将多条数据线充电到预定电压。 电路可以被配置为从存储器读取数据值，并将数据值传送到多条数据线。 多个预充电电路可以被配置为保持多个数据线上的数据。 电路可以选择维护的数据的第一子集，由存储器接收第二读取命令和第二地址，并且响应于第二地址对应于给定页面的确定来选择维护的数据的第二子集。