公开(公告)号：US11258446B2

公开(公告)日：2022-02-22

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K19/094 ,  H03K17/284 ,  G06F1/10

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US20200313660A1

公开(公告)日：2020-10-01

申请号：US16804675

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

公开(公告)号：US10903824B2

公开(公告)日：2021-01-26

申请号：US16804675

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

公开(公告)号：US20210344344A1

公开(公告)日：2021-11-04

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K19/094 ,  G06F1/10 ,  H03K17/284

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US10581412B1

公开(公告)日：2020-03-03

申请号：US16369072

申请日：2019-03-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.