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    Display with Silicon Gate Drivers and Semiconducting Oxide Pixels
    1.
    发明申请
    Display with Silicon Gate Drivers and Semiconducting Oxide Pixels 有权

    公开(公告)号：US20240420646A1

    公开(公告)日：2024-12-19

    申请号：US18815723

    申请日：2024-08-26

    Applicant: Apple Inc.

    Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chen-Ming Chen ,  Hassan Edrees

    IPC: G09G3/3266

    Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. The pixels can be formed using semiconducting oxide transistors, whereas the gate drivers can be formed using silicon transistor. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.

    Electronic display with hybrid in-pixel and external compensation
    4.
    发明授权
    Electronic display with hybrid in-pixel and external compensation 有权

    公开(公告)号：US11887546B2

    公开(公告)日：2024-01-30

    申请号：US18192905

    申请日：2023-03-30

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

    IPC: G09G3/3258 ,  H01L29/786 ,  H10K59/121

    CPC classification number: G09G3/3258 ,  H01L29/7869 ,  H10K59/1213 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

    Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

    Displays with reduced temperature luminance sensitivity
    6.
    发明授权
    Displays with reduced temperature luminance sensitivity 有权

    公开(公告)号：US11508309B2

    公开(公告)日：2022-11-22

    申请号：US17317128

    申请日：2021-05-11

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

    IPC: G09G3/3266

    Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

    Methods and apparatus for accelerating scan signal fall time to reduce display border width
    7.
    发明授权
    Methods and apparatus for accelerating scan signal fall time to reduce display border width 有权

    公开(公告)号：US11348533B1

    公开(公告)日：2022-05-31

    申请号：US16864241

    申请日：2020-05-01

    Applicant: Apple Inc.

    Inventor： Shinya Ono ,  Chin-Wei Lin ,  Gihoon Choo ,  Shiping Shen ,  Jie Won Ryu ,  Zino Lee ,  Hassan Edrees ,  Ting-Kuo Chang

    IPC: G09G3/3266

    Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The thin-film transistors may be controlled using at least first and second horizontal scan line signals. Loading different data values into any given row in the array may cause the scan line signals to exhibit varying rise/fall times, which results in horizontal crosstalk and luminance non-uniformity across the display. The rise and fall times of the second scan line signal are crucial, so the second scan line signal is driven by two separate scan line drivers formed on both sides of the display. Only the fall time of the first scan line signal is crucial, so the first scan line signal is driven by only one peripheral scan line driver and is coupled to an auxiliary pull-down circuit that is only activated during the pull-down transition.

    Electronic devices with low refresh rate display pixels
    9.
    发明授权
    Electronic devices with low refresh rate display pixels 有权

    公开(公告)号：US11257426B2

    公开(公告)日：2022-02-22

    申请号：US17080685

    申请日：2020-10-26

    Applicant: Apple Inc.

    Inventor： Chin-Wei Lin ,  Shyuan Yang ,  Chuang Qian ,  Abbas Jamshidi Roudbari ,  Ting-Kuo Chang

    IPC: G06F3/00 ,  G09G3/3225 ,  G09G3/3233

    Abstract: A display may have an array of organic light-emitting diode display pixels operating at a low refresh rate. Each display pixel may have six thin-film transistors and one capacitor. One of the six transistors may serve as the drive transistor and may be compensated using the remaining five transistors and the capacitor. One or more on-bias stress operations may be applied before threshold voltage sampling to mitigate first frame dimming. Multiple anode reset and on-bias stress operations may be inserted during vertical blanking periods to reduce flicker and maintain balance and may also be inserted between successive data refreshes to improve first frame performance. Two different emission signals controlling each pixel may be toggled together using a pulse width modulation scheme to help provide darker black levels.

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