公开(公告)号：US11251024B2

公开(公告)日：2022-02-15

申请号：US16933926

申请日：2020-07-20

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei Tseng ,  Casey Jane Madsen ,  Yikai Chen ,  Irena Wysok ,  Halbert Chong

IPC: H01J37/32 ,  C23C14/06 ,  C23C14/35 ,  H01J37/34 ,  C23C14/34

Abstract: Embodiments generally relate to a chamber component to be used in plasma processing chambers for semiconductor or display processing. In one embodiment, a chamber component includes a textured surface having a surface roughness ranging from about 150 microinches to about 450 microinches and a coating layer disposed on the textured surface. The coating layer may be a silicon layer having a purity ranging from about 90 weight percent to about 99 weight percent, a thickness ranging from about 50 microns to about 500 microns, and an electrical resistivity ranging from about 1 E-3 ohm*m to about 1 E3 ohm*m. The coating layer provides strong adhesion for materials deposited in the plasma processing chamber, which reduces the materials peeling from the chamber component. The coating layer also enables oxygen plasma cleaning for further reducing materials deposited on the chamber component and provides the protection of the textured surface located therebelow.

公开(公告)号：US10756259B2

公开(公告)日：2020-08-25

申请号：US16290621

申请日：2019-03-01

Applicant: Applied Materials, Inc.

Inventor： Jaesoo Ahn ,  Chando Park ,  Hsin-wei Tseng ,  Lin Xue ,  Mahendra Pakala

IPC: H01L27/00 ,  H01L43/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22

Abstract: The bottom-pinned spin-orbit torque (SOT) MRAM devices are fabricated to form high quality interfaces between layers including the spin-orbit torque (SOT) layer and the free layer of the magnetic tunnel junction (MTJ) by forming those layers under vacuum, without breaking vacuum in between formation of the layers. An encapsulation layer is used as an etch stop and to protect the free layer. The encapsulation layer is etched back prior to the deposition of a metal layer. The metal layer forms a plurality of metal lines that are electrically connected to two or more sides of the SOT layer and are electrically coupled to the SOT layer to transfer current through the SOT layer. The metal lines are not in contact with a top surface of the SOT layer which has a dielectric layer disposed thereon.

公开(公告)号：US12075628B2

公开(公告)日：2024-08-27

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Chando Park ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

CPC classification number: H10B61/00 ,  G11C11/161 ,  H10N50/80 ,  H10N50/85 ,  H10N50/01

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US11818959B2

公开(公告)日：2023-11-14

申请号：US17379780

申请日：2021-07-19

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei Tseng ,  Chando Park ,  Jaesoo Ahn ,  Lin Xue ,  Mahendra Pakala

IPC: H10N50/85 ,  H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for hybrid (or called integrated) spin-orbit-torque magnetic spin-transfer-torque magnetic random access memory (SOT-STT MRAM) applications. In one embodiment, the method includes one or more magnetic tunnel junction structures disposed on a substrate, the magnetic tunnel junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a spin orbit torque (SOT) layer disposed on the magnetic tunnel junction structure, and a back end structure disposed on the spin orbit torque (SOT) layer.

公开(公告)号：US11374170B2

公开(公告)日：2022-06-28

申请号：US16141470

申请日：2018-09-25

Applicant: Applied Materials, Inc.

Inventor： Lin Xue ,  Jaesoo Ahn ,  Hsin-wei Tseng ,  Mahendra Pakala

IPC: H01L43/12 ,  H01L43/10

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.

公开(公告)号：US11239086B2

公开(公告)日：2022-02-01

申请号：US16396226

申请日：2019-04-26

Applicant: Applied Materials, Inc.

Inventor： Hsin-wei Tseng ,  Mahendra Pakala ,  Lin Xue ,  Jaesoo Ahn ,  Sajjad Amin Hassan

IPC: H01L21/306 ,  H01L23/544 ,  H01L21/822 ,  G03F9/00

Abstract: Embodiments described herein relate to substrate processing methods. More specifically, embodiments of the disclosure provide for an MRAM back end of the line integration process which utilizes a zero mark for improved patterning alignment. In one embodiment, the method includes fabricating a substrate having at least a bottom contact and a via extending from the bottom contact in a first region and etching a zero mark in the substrate in a second region apart from the first region. The method also includes depositing a touch layer over the substrate in the first region and the second region, depositing a memory stack over the touch layer in the first region and the second region, and depositing a hardmask over the memory stack layer in the first region and the second region.