公开(公告)号：US20210026554A1

公开(公告)日：2021-01-28

申请号：US16521723

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Andrew John TURNER ,  Alex James WAUGH ,  Geoffray LACOURBA ,  Fergus Wilson MACGARRY

IPC: G06F3/06

Abstract: An interconnect apparatus comprises first node circuitry for performing first node operations to service data access requests in respect of a first range of memory addresses and second node circuitry for performing second node operations to service data access requests in respect of a second range of memory addresses. The interconnect comprises interface circuitry to: receive a retry indication in respect of a data access request from the first node and forward the retry indication to the requester circuitry; responsive to determining that the interface circuitry has capacity for the data access request, transmit a reissue capacity message to the requester circuitry; receive a reissued data access request from the requester circuitry; and issue the reissued data access request to the second node circuitry. The second node circuitry is responsive to receiving the reissued data access request to service the data access request.

公开(公告)号：US20180225216A1

公开(公告)日：2018-08-09

申请号：US15427421

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Alex James WAUGH ,  Geoffray LACOURBA ,  Paul Gilbert MEYER ,  Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA

IPC: G06F12/0862 ,  G06F15/78

CPC classification number: G06F12/0862 ,  G06F11/34 ,  G06F12/0811 ,  G06F12/0833 ,  G06F15/7825 ,  G06F2212/502 ,  G06F2212/507

Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.

公开(公告)号：US20230244606A1

公开(公告)日：2023-08-03

申请号：US17592022

申请日：2022-02-03

Applicant: Arm Limited

Inventor： Geoffray LACOURBA ,  Luca NASSI ,  Damien CATHRINE ,  Stefano GHIGGINI ,  Albin Pierrick TONNERRE

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: Circuitry comprises a memory system to store data items; cache memory storage to store a copy of one or more data items, the cache memory storage comprising a hierarchy of two or more cache levels; detector circuitry to detect at least a property of data items for storage by the cache memory storage; and control circuitry to control eviction, from a given cache level, of a data item stored by the given cache level, the control circuitry being configured to select a destination to store a data item evicted from the given cache level in response to a detection by the detector circuitry.