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公开(公告)号：US20240169644A1
公开(公告)日：2024-05-23
申请号：US18509426
申请日：2023-11-15
Applicant: Arm Limited
Inventor： Tord Kvestad Øygard , Sandeep Kakarlapudi , Toni Viki Brkic , William Robert Stoye
CPC classification number: G06T15/005 , G06T11/40
Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information comprises the depth buffer.
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公开(公告)号：US20240037692A1
公开(公告)日：2024-02-01
申请号：US18357461
申请日：2023-07-24
Applicant: Arm Limited
Inventor： William Robert Stoye , Olof Henrik Uhrenholt , Wing-Tsi Henry Wong , Edward Hardy , Toni Viki Brkic , Ole Magnus Ruud
CPC classification number: G06T1/20 , G06T11/001
Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry including, inter alia, at least an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents, and an indication of whether the group of fragments that the list entry represents is eligible to undergo particular processing operations. The coverage information and eligibility information for the list entries is then used to control the processing of fragments for sub-regions of a tile, in such a way as to ensure that processing order dependencies are enforced and met.
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公开(公告)号：US20240037853A1
公开(公告)日：2024-02-01
申请号：US18357481
申请日：2023-07-24
Applicant: Arm Limited
Inventor： William Robert Stoye , Olof Henrik Uhrenholt , Wing-Tsi Henry Wong , Edward Hardy , Toni Viki Brkic , Ole Magnus Ruud
Abstract: When performing tile-based rendering in a graphics processing system, lists indicative of fragments to be processed are maintained for respective sub-regions of tiles to be rendered, with each list entry representing a group of one or more fragments and including an indication of the coverage within the tile sub-region of the group of fragments that the list entry represents. The coverage information for the list entries is then used to set for entries in the list indicative of fragments to be processed for a sub-region, information indicating whether one or more processing operations are eligible to be performed for fragments that entries in the list represent.
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公开(公告)号：US10290132B2
公开(公告)日：2019-05-14
申请号：US15075465
申请日：2016-03-21
Applicant: ARM Limited
Inventor： William Robert Stoye , Samuel Martin
Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.
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公开(公告)号：US20160284043A1
公开(公告)日：2016-09-29
申请号：US15075465
申请日：2016-03-21
Applicant: ARM Limited
Inventor： William Robert Stoye , Samuel Martin
IPC: G06T1/20
Abstract: A graphics processor performs interleaved graphics processing wherein the interleaved graphics processing comprises performing one or more processing operations to generate one or more sub-regions of a first set of graphics data, and performing one or more further processing operations to generate one or more sub-regions of a second set of graphics data that are dependent on the one or more sub-regions of the first set of graphics data prior to performing one or more processing operations to generate one or more further sub-regions of the first set of graphics data.
Abstract translation: 图形处理器执行交织的图形处理，其中交织的图形处理包括执行一个或多个处理操作以生成第一组图形数据的一个或多个子区域，以及执行一个或多个另外的处理操作以生成一个或多个子图像， 在执行一个或多个处理操作之前依赖于第一组图形数据的一个或多个子区域的第二组图形数据的区域，以生成第一组图形数据的一个或多个另外的子区域 。
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Patent Agency Ranking
公开(公告)号：US20220392146A1
公开(公告)日：2022-12-08
申请号：US17805387
申请日：2022-06-03
Applicant: Arm Limited
Inventor： Richard Bruce , William Robert Stoye , Mathieu Jean Joseph Robart , Jørn Nystad
Abstract: There is provided an instruction, or instructions, that can be included in a program to perform a ray tracing operation, with individual execution threads in a group of execution threads executing the program performing the ray tracing operation for a respective ray in a corresponding group of rays such that the group of rays performing the ray tracing operation together. The instruction(s), when executed by the execution threads will cause one or more rays from the group of plural rays to be tested for intersection with a set of primitives. A result of the ray-primitive intersection testing can then be returned for the traversal operation.
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公开(公告)号：US11276137B1
公开(公告)日：2022-03-15
申请号：US17201229
申请日：2021-03-15
Applicant: Arm Limited
Inventor： Isidoros Sideris , Stephane Forey , William Robert Stoye , John David Robson
Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.
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公开(公告)号：US11016774B1
公开(公告)日：2021-05-25
申请号：US16695917
申请日：2019-11-26
Applicant: Arm Limited
Inventor： Luka Dejanovic , William Robert Stoye
Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.
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公开(公告)号：US20240371070A1
公开(公告)日：2024-11-07
申请号：US18602592
申请日：2024-03-12
Applicant: Arm Limited
Inventor： Jakob Axel Fries , William Robert Stoye , Richard Edward Bruce
Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray tracing circuit of the graphics processor may require additional storage space to store test record entries to trace a ray, additional storage space is allocated for the ray tracing circuit to use to store test record entries to trace the ray.
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公开(公告)号：US20210157600A1
公开(公告)日：2021-05-27
申请号：US16695917
申请日：2019-11-26
Applicant: Arm Limited
Inventor： Luka Dejanovic , William Robert Stoye
Abstract: A data processor is disclosed in which groups of execution threads can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. Two or more execution threads of a thread group are issued to the same execution lane for execution. The two or more execution threads can then be processed by the execution lane successively, such that the execution lane performs the same processing operation successively. This can have the effect of reducing signal transitions, such that the overall energy consumption of the data processor can be reduced.
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