公开(公告)号：US20230176983A1

公开(公告)日：2023-06-08

申请号：US17906625

申请日：2021-01-26

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1045 ,  G06F12/0808

CPC classification number: G06F12/1425 ,  G06F12/1458 ,  G06F12/1063 ,  G06F12/0808

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

公开(公告)号：US20230140975A1

公开(公告)日：2023-05-11

申请号：US17906815

申请日：2021-02-05

Applicant: Arm Limited

Inventor： Yuval ELAD ,  Jason PARKER

IPC: G06F21/78 ,  G06F21/60 ,  G06F21/54

CPC classification number: G06F21/78 ,  G06F21/606 ,  G06F21/54

Abstract: There is provided a data processing apparatus, which is suitable for verifying memory systems. Processing circuitry issues a plurality of memory access requests to a plurality of addresses in a memory. Point-of-trust circuitry receives the memory access requests from the processing circuitry via a first set of intermediate circuits. Secure channel circuitry enables secure communication of a correspondence between the plurality of addresses from the processing circuitry to the point-of-trust circuitry. The point-of-trust circuitry determines whether the addresses in the memory of the memory access requests received via the first set of intermediate circuits have a predetermined relationship based on the correspondence.

公开(公告)号：US20230342303A1

公开(公告)日：2023-10-26

申请号：US17998744

申请日：2021-05-14

Applicant: ARM LIMITED

Inventor： Richard Roy GRISENTHWAITE ,  Jason PARKER ,  Mark Salling RUTLAND ,  Yuval ELAD

IPC: G06F12/1045 ,  G06F12/14

CPC classification number: G06F12/1045 ,  G06F12/14 ,  G06F2212/1052

Abstract: An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.

公开(公告)号：US20230132695A1

公开(公告)日：2023-05-04

申请号：US17906581

申请日：2021-01-26

Applicant: Arm Limited

Inventor： Jason PARKER ,  Yuval ELAD

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/109

Abstract: Processing circuitry (10) performs processing in one of at least three domains (82, 84, 86, 88). Address translation circuitry (16) translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces (61) selected based at least on the current domain. The domains include a root domain (82) for managing switching between other domains. The physical address spaces (61) include a root physical address space associated with the root domain (82), separate from physical address spaces associated with other domains.

公开(公告)号：US20210303683A1

公开(公告)日：2021-09-30

申请号：US16829390

申请日：2020-03-25

Applicant: Arm Limited

Inventor： Yuval ELAD

IPC: G06F21/55 ,  G06F11/10

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, a cache storage, victim row identification circuitry and victim row protection circuitry. The victim row identification circuitry is configured to detect a rapid rate of access requests from the processing circuitry to a given row of a DRAM and, responsive to said detecting, identify at least one victim row associated with said given row. The victim row protection circuitry is configured to copy data stored within said at least one victim row to the cache storage.

公开(公告)号：US20250036575A1

公开(公告)日：2025-01-30

申请号：US18914382

申请日：2024-10-14

Applicant: Arm Limited

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/109

Abstract: Processing circuitry 10 performs processing in one of at least three domains 82, 84, 86, 88. Address translation circuitry 16 translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces 61 selected based at least on the current domain. The domains include a root domain 82 for managing switching between other domains. The physical address spaces 61 include a root physical address space associated with the root domain 82, separate from physical address spaces associated with other domains.

公开(公告)号：US20230236987A1

公开(公告)日：2023-07-27

申请号：US17907178

申请日：2021-03-08

Applicant: ARM LIMITED

Inventor： Yuval ELAD ,  Richard Roy GRISENTHWAITE ,  Jason PARKER ,  Simon John CRASKE ,  Alexander Donald Charles CHADWICK

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F12/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: Apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

公开(公告)号：US20230205709A1

公开(公告)日：2023-06-29

申请号：US17996269

申请日：2021-04-14

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Yuval ELAD ,  Alexander Donald Charles CHADWICK ,  Andrew Brookfield SWAINE ,  Carlos GARCIA-TOBIN

IPC: G06F12/14

CPC classification number: G06F12/1483 ,  G06F12/1441 ,  G06F12/145

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

公开(公告)号：US20220318140A1

公开(公告)日：2022-10-06

申请号：US17218718

申请日：2021-03-31

Applicant: Arm Limited

Inventor： Steven Douglas KRUEGER ,  Yuval ELAD

IPC: G06F12/0802 ,  G06F3/06

Abstract: Processing circuitry processes instructions in one of at least three domains each associated with a corresponding physical address space, and issues a memory access request to a memory system, the memory access request comprising a partition identifier (selected based on programmable partition identifier selection information associated with a current software execution environment which caused the memory access request to be issued) and a multi-bit partition identifier space indicator indicating a selected partition identifier space (selected from among at least three partition identifier spaces based on a current domain of the processing circuitry). The selected partition identifier space and partition identifier together represent information for selecting, at a memory system component, parameters for controlling allocation of resources for handling the memory access request or managing contention for said resources, or for selecting whether performance monitoring data is updated in response to the memory access request.

公开(公告)号：US20210311640A1

公开(公告)日：2021-10-07

申请号：US17269919

申请日：2019-10-17

Applicant: Arm Limited

Inventor： Yuval ELAD ,  Roberto AVANZI ,  Jason PARKER

IPC: G06F3/06 ,  G06F12/1009 ,  G06F16/901

Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.