公开(公告)号：US20230421116A1

公开(公告)日：2023-12-28

申请号：US17847733

申请日：2022-06-23

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Gary M. Madison

IPC: H03F3/08 ,  H03F1/08 ,  H03F3/45

CPC classification number: H03F3/082 ,  H03F3/085 ,  H03F1/086 ,  H03F3/45475 ,  H03F2200/451

Abstract: Techniques are provided for a transimpedance amplifier (TIA). A TIA implementing the techniques according to an embodiment includes a pre-amplifier stage configured to amplify an input signal. The pre-amplifier stage includes a first P-channel metal oxide semiconductor field effect transistor (MOSFET) (P1), a second P-channel MOSFET (P2), a first N-channel MOSFET (N1), and a second N-channel MOSFET (N2), coupled in series. The gates of P1 and N2 are driven by the input signal. The output of the pre-amplifier stage is provided at a coupling between the drain of P2 and the drain of N1. The pre-amplifier stage also includes an active resistor network configured to provide a variable resistance based on a provided current bias generated from a gain control signal. The active resistor network is coupled between the gate of P1 and the drain of P2. The variable resistance is used to control the gain of the pre-amplifier stage.

公开(公告)号：US20250111881A1

公开(公告)日：2025-04-03

申请号：US18477058

申请日：2023-09-28

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Gary M. Madison ,  Kevin Grout

IPC: H03K17/687 ,  H03K17/60 ,  H03K19/0175

Abstract: A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.

公开(公告)号：US20210258001A1

公开(公告)日：2021-08-19

申请号：US16571620

申请日：2019-09-16

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Gary M. Madison

IPC: H03K5/00 ,  H03K3/037

Abstract: A CMOS divide by two circuit device comprising a two phase signal input, a first track and hold circuit, a second track and hold circuit, where the signal path from input to output of each track and hold circuit comprises a single switch and a single inverter. In hold mode the circuit device provides cross-coupled inverters with only two stable states, obviating the need for any dedicated start-up, initialization, or phase-forcing circuitry. In addition to its regular two-phase output, it can optionally provide a quadrature two-phase output, both having an output signal frequency equal to one half said input signal frequency.

公开(公告)号：US11012079B1

公开(公告)日：2021-05-18

申请号：US16721494

申请日：2019-12-19

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Joseph D. Cali ,  Curtis M. Grens ,  Richard L. Harwood ,  Gary M. Madison

IPC: H03L7/099 ,  H03L7/107 ,  H03L7/093

Abstract: A phase locked loop (PLL) control system includes a voltage-controlled oscillator (VCO) circuit including an inductor and a plurality of capacitors arranged in parallel with the inductor. Digitally enabling or disabling the capacitors in a thermometer coded manner via switches creates tuning states that provide additional frequency range, and each has a limited range of VCO frequency tuning. Slowly ramping the switched capacitance, by implementing the capacitor as a varactor, from one thermal code to the next, provides a wider continuous VCO frequency tuning range for use in the PLL. The slow transition between tuning states allows the PLL to remain in lock, useful under changing operating conditions. Specifically, under changing operating conditions, digital logic detects the PLL tuning control voltage approaching the edge of a VCO band and will add/reduce VCO capacitance effectively transitioning into the adjacent VCO band while the PLL maintains lock via its normal feedback loop.

公开(公告)号：US20200328749A1

公开(公告)日：2020-10-15

申请号：US16383179

申请日：2019-04-12

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Gary M. Madison

IPC: H03L7/089 ,  H03L7/08 ,  H03L7/099

Abstract: A phase-frequency detector has two latches, two logic gates, and two delay sources. Operation includes inputting a reference clock signal to a first of two latches; inputting a feedback clock signal to a second of two latches; outputting simultaneously a first signal and a second signal. The first signal having a pulse width directly proportional to a phase difference between said reference clock signal and the feedback clock signal; the second signal having a pulse width inversely proportional to the phase difference between the reference clock signal and the feedback clock signal. The outputs of the latches indicate a differential phase difference of signals, thereby increasing the signal-to noise ratio of the phase-frequency detector.

公开(公告)号：US12288587B2

公开(公告)日：2025-04-29

申请号：US18477058

申请日：2023-09-28

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Gary M. Madison ,  Kevin Grout

IPC: G11C27/02 ,  H03K17/60 ,  H03K17/687 ,  H03K19/0175

Abstract: A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.

公开(公告)号：US20250030393A1

公开(公告)日：2025-01-23

申请号：US18354354

申请日：2023-07-18

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jonathan P. Comeau ,  Douglas S. Jansen ,  Gary M. Madison

IPC: H03H7/25 ,  H03H11/24

Abstract: An attenuator circuit includes a differential input having first and second inputs, and a differential output having first and second outputs. The attenuator circuit further includes a first transistor coupled between the first input and the first output, a second transistor coupled between the second input and the second output, a third transistor coupled between the first input and the second output, and a fourth transistor coupled between the second input and the first output. During a pass-through state, the first and second transistors are enabled, and the third and fourth transistors may be disabled. During an attenuation state, the first, second, third, and fourth transistors are all disabled. An attenuator network (e.g., T or Pi network) may have its differential input terminals coupled to the first and second inputs of the differential input, and its differential output terminals coupled to the first and second outputs of the differential output.