公开(公告)号：US3904449A

公开(公告)日：1975-09-09

申请号：US46851974

申请日：1974-05-09

Applicant: BELL TELEPHONE LABOR INC

Inventor： DILORENZO JAMES VINCENT ,  LUTHER LARS CHRISTIAN

IPC: H01L29/864 ,  H01L7/36

CPC classification number: H01L29/864 ,  Y10S148/056 ,  Y10S148/057 ,  Y10S148/067 ,  Y10S148/129 ,  Y10S148/139

Abstract: High efficiency GaAs Schottky barrier IMPATT diodes comprising a non-uniformly doped depletion region are fabricated by instantaneously injecting a known volume of a known concentration of dopant at a known pressure during chemical vapor deposition epitaxial growth of the n layer forming the depletion region. This technique has yielded n layers 150 Angstroms thick, doped to carrier concentration values as high as 1018 cm 3, with precise control of the position of the n layer within the depletion region.

Abstract translation: 包含非均匀掺杂的耗尽区的高效GaAs肖特基势垒IMPATT二极管通过在形成耗尽区的n层的化学气相沉积外延生长期间以已知的压力瞬时注入已知体积的已知浓度的掺杂剂来制造。 这种技术已经产生了150埃厚的n +层，掺杂到高达1018厘米3的载流子浓度值，精确控制了耗尽区内n +层的位置。

公开(公告)号：US3896473A

公开(公告)日：1975-07-22

申请号：US42152173

申请日：1973-12-04

Applicant: BELL TELEPHONE LABOR INC

Inventor： DILORENZO JAMES VINCENT ,  NIEHAUS WILLIAM CHARLES ,  RODE DANIEL LEON

IPC: H01L23/36 ,  H01L25/03 ,  H01L29/00 ,  H01L29/864 ,  H01L1/12 ,  H01L1/18

CPC classification number: H01L29/864 ,  H01L23/36 ,  H01L25/03 ,  H01L29/00 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Gallium arsenide power dissipating devices are described, which comprise an array of mesas formed on a plated heat sink in order to reduce thermal effects. The array is connected in parallel with beam leads to permit thermocompression bonding to only one of the mesas and thus reduce the number of bonding operations. Bonding stresses to the device may be eliminated by rendering one of the mesas inactive.

公开(公告)号：US3890215A

公开(公告)日：1975-06-17

申请号：US44066474

申请日：1974-02-08

Applicant: BELL TELEPHONE LABOR INC

Inventor： DILORENZO JAMES VINCENT ,  NIEHAUS WILLIAM CHARLES ,  RODE DANIEL LEON ,  SCHWARTZ BERTRAM

IPC: H01L21/3063 ,  H01L21/316 ,  H01L29/00 ,  B23P1/00 ,  H01L7/00

CPC classification number: H01L21/31679 ,  H01L21/02241 ,  H01L21/02258 ,  H01L21/3063 ,  H01L21/30635 ,  H01L29/00 ,  Y10S438/977

Abstract: A method for precisely tailoring the thickness of a layer of semiconductor material in a structure comprising regions of varying doping concentrations in order to achieve desired uniform electrical properties. The method involves, generally, electrolytically thinning the layer to remove the semiconductor material until a desired field distribution in the structure is reached. In one embodiment, an FET with an epitaxial layer on a semi-insulating substrate is manufactured by successively oxidizing the epitaxial layer and dissolving the oxide until the depletion region resulting from the applied potential extends into the semi-insulating substrate and oxide growth stops. This results in a uniform pinch-off condition along the layer regardless of the original non-uniformity in the epitaxial layer. In a further embodiment, the epitaxial layer in an IMPATT structure is thinned by successive oxidation and dissolution until the voltage dropped across the semiconductor is equal to the applied potential and again oxide growth stops. This procedure results in a desired uniform breakdown voltage for the wafer.

Abstract translation: 一种用于在包括改变掺杂浓度的区域的结构中精确地定制半导体材料层的厚度的方法，以便实现期望的均匀电性能。 通常，该方法通常电解稀薄该层以去除半导体材料，直到达到结构中的期望的场分布。 在一个实施例中，在半绝缘衬底上具有外延层的FET通过连续地氧化外延层并溶解氧化物来制造，直到由所施加的电势产生的耗尽区延伸到半绝缘衬底中并且氧化物生长停止。 这导致沿着该层的均匀夹断条件，而不管外延层中的原始不均匀性如何。 在另一个实施方案中，通过连续的氧化和溶解使IMPATT结构中的外延层变薄，直到跨过半导体的电压下降等于所施加的电势，并且再次氧化物生长停止。 该过程导致晶片所需的均匀击穿电压。