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    Synchronization and training stage operation
    1.
    发明授权
    Synchronization and training stage operation 有权

    公开(公告)号：US10027471B2

    公开(公告)日：2018-07-17

    申请号：US14795840

    申请日：2015-07-09

    申请人： BROADCOM CORPORATION

    发明人： Chung Ming Tu ,  Peiqing Wang ,  Ahmad Chini ,  Yencheng Chen ,  Mehmet Vakif Tazebay ,  Bazhong Shen

    IPC分类号： H04L7/10 ,  H04L12/413 ,  H04L7/04

    摘要： A primary device implementing the subject system of link establishment for single pair Ethernet may include at least one processor circuit. The at least one processor circuit may be configured to transmit a first synchronization sequence to a secondary device and to subsequently detect a second synchronization sequence, different than the first, transmitted by the secondary device. The synchronization sequences may be pseudo-noise sequences that have strong autocorrelation characteristics. The at least one processor circuit may be configured to wait a predetermined amount of time after completing the detection of the second synchronization sequence, and then may initiate a training stage. The training stage may include exchanging scrambler states of additive scramblers used by the primary and secondary devices. The at least one processor circuit may be configured to enter a data mode upon completion of training. In the data mode, data is forward error correction encoded and then scrambled.

    Robust Line Coding Scheme for Communication Under Severe External Noises
    2.
    发明申请
    Robust Line Coding Scheme for Communication Under Severe External Noises 有权
    严重外部噪声下的通信鲁棒线路编码方案

    公开(公告)号：US20150326348A1

    公开(公告)日：2015-11-12

    申请号：US14705608

    申请日：2015-05-06

    申请人： Broadcom Corporation

    发明人： Ba-Zhong Shen ,  Ahmad Chini ,  Chung Ming Tu ,  Mehmet Vakif Tazebay

    IPC分类号： H04L1/00 ,  H04L29/08 ,  H04L27/04

    CPC分类号： H04L1/0041 ,  H04L1/0042 ,  H04L25/4917 ,  H04L27/04 ,  H04L67/12

    摘要： A system to implement a communication line coding scheme using a non-complex bit-to-symbol mapping, a forward error correction (FEC) coding, and an additive bit scrambler after the FEC at the PHY layer is provided. The system may be a part of or implemented by an automobile component. The system may be a PHY device configured to convert data from the MAC layer into 2D-PAM3 symbols that are transmitted across a communication link at a predetermined transmission rate, such as to be compliant with a communication standard. The PHY device may select characteristics of the conversion, such as the FEC coded symbol, based on the target transmission rate. The PHY device may include a transceiver, and may convert the data from MAC layer to PHY layer and back.

    摘要翻译： 提供了在PHY层之后，在FEC之后实现使用非复杂比特对符号映射，前向纠错（FEC）编码和附加比特加扰器的通信线路编码方案的系统。 该系统可以是汽车部件的一部分或由汽车部件实现。 该系统可以是被配置为将来自MAC层的数据转换为以预定传输速率通过通信链路传输的2D-PAM3符号的PHY设备，例如符合通信标准。 PHY设备可以基于目标传输速率来选择转换的特性，例如FEC编码符号。 PHY设备可以包括收发器，并且可以将数据从MAC层转换为PHY层并返回。

    Two-dimensional (2D) decision feedback equalizer (DFE) slicer within communication systems
    4.
    发明授权
    Two-dimensional (2D) decision feedback equalizer (DFE) slicer within communication systems 有权
    通信系统中的二维（2D）判决反馈均衡器（DFE）限幅器

    公开(公告)号：US09553743B2

    公开(公告)日：2017-01-24

    申请号：US14834615

    申请日：2015-08-25

    申请人： BROADCOM CORPORATION

    发明人： Ba-Zhong Shen ,  Mehmet Vakif Tazebay ,  Chung Ming Tu

    IPC分类号： H04L25/06 ,  H04L25/03

    CPC分类号： H04L25/066 ,  H04L25/03057 ,  H04L25/03146

    摘要： A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. For example, the device's processor receives one or more signals from a communication channel. The processor then processes the one or more signals to generate 2D DFE soft slicer outputs and to decode the one or more signals based on the 2D DFE soft slicer outputs to generate estimates of information encoded within the one or more signals. The processor may process the 2D DFE soft slicer outputs to generate 2D DFE hard decisions and then generates other estimates of the information encoded based on the 2D DFE hard decisions.

    摘要翻译： 通信设备（可选地，设备）包括被配置为支持与其他通信设备的通信并且生成和处理用于这种通信的信号的处理器。 在一些示例中，设备包括通信接口和处理器以及其他可能的电路，组件，元件等，以支持与其他通信设备的通信，并且生成和处理用于这种通信的信号。 例如，设备的处理器从通信信道接收一个或多个信号。 然后，处理器处理一个或多个信号以产生2D DFE软限幅器输出，并且基于2D DFE软限幅器输出对一个或多个信号进行解码，以产生在一个或多个信号内编码的信息的估计。 处理器可以处理2D DFE软切片器输出以产生2D DFE硬判决，然后生成基于2D DFE硬判决编码的信息的其他估计。

    Two-dimensional (2D) decision feedback equalizer (DFE) slicer within communication systems
    6.
    发明申请
    Two-dimensional (2D) decision feedback equalizer (DFE) slicer within communication systems 有权
    通信系统中的二维（2D）判决反馈均衡器（DFE）限幅器

    公开(公告)号：US20160056981A1

    公开(公告)日：2016-02-25

    申请号：US14834615

    申请日：2015-08-25

    申请人： BROADCOM CORPORATION

    发明人： Ba-Zhong Shen ,  Mehmet Vakif Tazebay ,  Chung Ming Tu

    IPC分类号： H04L25/03

    CPC分类号： H04L25/066 ,  H04L25/03057 ,  H04L25/03146

    摘要： A communication device (alternatively, device) includes a processor configured to support communications with other communication device(s) and to generate and process signals for such communications. In some examples, the device includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other communication device(s) and to generate and process signals for such communications. For example, the device's processor receives one or more signals from a communication channel. The processor then processes the one or more signals to generate 2D DFE soft slicer outputs and to decode the one or more signals based on the 2D DFE soft slicer outputs to generate estimates of information encoded within the one or more signals. The processor may process the 2D DFE soft slicer outputs to generate 2D DFE hard decisions and then generates other estimates of the information encoded based on the 2D DFE hard decisions.

    摘要翻译： 通信设备（可选地，设备）包括被配置为支持与其他通信设备的通信并且生成和处理用于这种通信的信号的处理器。 在一些示例中，设备包括通信接口和处理器以及其他可能的电路，组件，元件等，以支持与其他通信设备的通信，并且生成和处理用于这种通信的信号。 例如，设备的处理器从通信信道接收一个或多个信号。 然后，处理器处理一个或多个信号以产生2D DFE软限幅器输出，并且基于2D DFE软限幅器输出对一个或多个信号进行解码，以产生在一个或多个信号内编码的信息的估计。 处理器可以处理2D DFE软切片器输出以产生2D DFE硬判决，然后生成基于2D DFE硬判决编码的信息的其他估计。