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    System and Method for Next Generation BASE-T Communication
    1.
    发明申请
    System and Method for Next Generation BASE-T Communication 有权
    下一代BASE-T通信的系统和方法

    公开(公告)号：US20130265895A1

    公开(公告)日：2013-10-10

    申请号：US13784936

    申请日：2013-03-05

    Applicant: BROADCOM CORPORATION

    Inventor： Wael William Diab ,  William Calvin Woodruff

    IPC: H04L12/24

    CPC classification number: H04L41/0896 ,  H04L41/0816 ,  H04L43/50

    Abstract: A system and method for next generation BASE-T communication. Next generation BASE-T devices designed for communication over twisted pair Ethernet cabling are configurable based on the characteristics of the communication channel. In discovering the characteristics of the communication channel, the physical layer device (PHY) can select one of a plurality of operating modes that can support a given data transmission rate (e.g., 10 Gbit/s, 40 Gbit/s, 100 Gbit/s, 400 Gbit/s, etc.).

    Abstract translation: 一种用于下一代BASE-T通信的系统和方法。 设计用于通过双绞线以太网电缆进行通信的下一代BASE-T设备可根据通信通道的特性进行配置。 在发现通信信道的特性时，物理层设备（PHY）可以选择能够支持给定数据传输速率的多种操作模式之一（例如，10Gbit / s，40Gbit / s，100Gbit / s ，400Gbit / s等）。

    Multi-chip module with a high-rate interface
    2.
    发明授权
    Multi-chip module with a high-rate interface 有权

    公开(公告)号：US09843538B2

    公开(公告)日：2017-12-12

    申请号：US14599411

    申请日：2015-01-16

    Applicant: BROADCOM CORPORATION

    Inventor： William Calvin Woodruff

    IPC: H04L12/935 ,  H04J3/04 ,  H04J3/06 ,  H04L12/741 ,  H04L12/931

    CPC classification number: H04L49/30 ,  H04J3/047 ,  H04J3/0697 ,  H04L45/745 ,  H04L49/40

    Abstract: A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

    LOW POWER TWISTED PAIR CODING SCHEME
    3.
    发明申请
    LOW POWER TWISTED PAIR CODING SCHEME 审中-公开
    低功率双绞配对方案

    公开(公告)号：US20150207635A1

    公开(公告)日：2015-07-23

    申请号：US14603055

    申请日：2015-01-22

    Applicant: Broadcom Corporation

    Inventor： Chung Ming TU ,  Alan Kwentus ,  William Calvin Woodruff

    IPC: H04L12/12 ,  H04L1/00 ,  H04L27/00

    CPC classification number: H04L12/12 ,  H04B3/32 ,  H04L1/0002 ,  H04L1/0057 ,  Y02D50/40

    Abstract: A transceiver, a communication system and an associated method thereof for reducing overall power consumption and complexity of the transceiver that operates over short reach twisted pair cables. The analog front end (AFE) of the transceiver communicates over at least one twisted pair that is configured only for transmission of data streams and communicates over at least one twisted pair that is only for reception of data streams. The transceiver includes circuitry that generates multiplexed and demultiplexed data streams for communication with the analog front end. Additionally, the transceiver utilizes at least certain portions of signal processing circuitry and AFE of a 10 GBASE-T transceiver or the like.

    Abstract translation: 收发器，通信系统及其相关联的方法，用于降低在短距离双绞线电缆上工作的收发器的总体功耗和复杂性。 收发器的模拟前端（AFE）通过至少一个双绞线进行通信，双绞线仅配置为传输数据流，并通过至少一个只用于接收数据流的双绞线进行通信。 收发器包括产生用于与模拟前端通信的多路复用和解复用的数据流的电路。 此外，收发器利用10GBASE-T收发器等的信号处理电路和AFE的至少某些部分。

    System and method for next generation BASE-T communication
    4.
    发明授权
    System and method for next generation BASE-T communication 有权
    用于下一代BASE-T通信的系统和方法

    公开(公告)号：US08934372B2

    公开(公告)日：2015-01-13

    申请号：US13784936

    申请日：2013-03-05

    Applicant: Broadcom Corporation

    Inventor： Wael William Diab ,  William Calvin Woodruff

    IPC: H04L12/26 ,  H04L12/28 ,  H04L12/24

    CPC classification number: H04L41/0896 ,  H04L41/0816 ,  H04L43/50

    Abstract: A system and method for next generation BASE-T communication. Next generation BASE-T devices designed for communication over twisted pair Ethernet cabling are configurable based on the characteristics of the communication channel. In discovering the characteristics of the communication channel, the physical layer device (PHY) can select one of a plurality of operating modes that can support a given data transmission rate (e.g., 10 Gbit/s, 40 Gbit/s, 100 Gbit/s, 400 Gbit/s, etc.).

    Abstract translation: 一种用于下一代BASE-T通信的系统和方法。 设计用于通过双绞线以太网电缆进行通信的下一代BASE-T设备可根据通信通道的特性进行配置。 在发现通信信道的特性时，物理层设备（PHY）可以选择能够支持给定数据传输速率的多种操作模式之一（例如，10Gbit / s，40Gbit / s，100Gbit / s ，400Gbit / s等）。

    Attachment unit interfaces for non-identical data rate links
    6.
    发明授权
    Attachment unit interfaces for non-identical data rate links 有权

    公开(公告)号：US09742701B2

    公开(公告)日：2017-08-22

    申请号：US14462498

    申请日：2014-08-18

    Applicant: BROADCOM CORPORATION

    Inventor： William Calvin Woodruff ,  Alan Kwentus ,  Chao Lin ,  Richard Dale Tidstrom

    IPC: H04L12/28 ,  H04L12/935 ,  H04L12/931

    CPC classification number: H04L49/30 ,  H04L49/352 ,  H04L49/356

    Abstract: An apparatus for operating a low data-rate (LDR) link and legacy switch at a high data-rate (HDR) includes a first block and a second block. The first block receives input signals from the legacy switch and generates identical output signals. The second block receives the identical output signals and generates an HDR signal for communication over the LDR link coupled to an access point. Further, a media access control (MAC) interface communicates data at a first data rate with an Ethernet PHY block including a first-in-first-out (FIFO) module and a buffer. The FIFO receives data from the MAC interface at the first data rate and transmits data at a second data rate. The buffer receives data from the Ethernet port at the second data rate and transmits the received data at the first data rate in response to detection of an end of packet.

    Method for implementing a multi-chip module with a high-rate interface
    7.
    发明授权
    Method for implementing a multi-chip module with a high-rate interface 有权
    用于实现具有高速率接口的多芯片模块的方法

    公开(公告)号：US08964772B2

    公开(公告)日：2015-02-24

    申请号：US13648227

    申请日：2012-10-09

    Applicant: Broadcom Corporation

    Inventor： William Calvin Woodruff

    IPC: H04L12/28

    CPC classification number: H04L49/30 ,  H04J3/047 ,  H04J3/0697 ,  H04L45/745 ,  H04L49/40

    Abstract: A multi-chip module (MCM) may include a substrate, and first and second physical-layer (PHY) chips mounted on the substrate. In some implementations, the first PHY chip includes a multiplexer and a PHY circuit. The multiplexer is configured to receive a multiplexed data stream from a media access control (MAC) device, to demultiplex the multiplexed data stream into first and second data streams, to output the first data stream to the PHY circuit, and to output the second data stream to the second PHY chip. In some implementations, the first PHY includes a router and a PHY circuit. The router is configured to receive a plurality of data packets from a MAC device, to route one or more of the data packets having a first address to the PHY circuit, and to route one or more of the data packets having a second address to the second PHY chip.

    Abstract translation: 多芯片模块（MCM）可以包括衬底以及安装在衬底上的第一和第二物理层（PHY）芯片。 在一些实现中，第一PHY芯片包括多路复用器和PHY电路。 复用器被配置为从媒体接入控制（MAC）设备接收复用的数据流，将多路复用的数据流解复用为第一和第二数据流，以将第一数据流输出到PHY电路，并输出第二数据 流到第二个PHY芯片。 在一些实现中，第一PHY包括路由器和PHY电路。 路由器被配置为从MAC设备接收多个数据分组，将具有第一地址的数据分组中的一个或多个路由到PHY电路，并且将具有第二地址的数据分组中的一个或多个路由到 第二PHY芯片。

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