公开(公告)号：US10103048B2

公开(公告)日：2018-10-16

申请号：US14472073

申请日：2014-08-28

Applicant: Brewer Science Inc.

Inventor： Tony D. Flaim ,  Jeremy McCutcheon

IPC: B32B38/10 ,  H01L21/683 ,  B32B37/14 ,  B32B37/30 ,  B32B43/00 ,  B32B37/24

Abstract: A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can potentially improve bond line stability during backside processing of temporarily bonded wafers, simplify the preparation of bonded wafers by eliminating the need for specialized release layers, and reduce wafer cleaning time and chemical consumption after debonding.

公开(公告)号：US09224631B2

公开(公告)日：2015-12-29

申请号：US14191544

申请日：2014-02-27

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/20 ,  H01L23/00 ,  B32B38/00 ,  B32B38/10 ,  B32B43/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract translation: 提供临时连接半导体衬底的多个结合层方案。 在本发明的接合方案中，至少一个层直接与半导体衬底接触，且该方案中的至少两个层彼此直接接触。 本发明提供了多个处理选择，因为多层结构内的不同层执行特定的功能。 更重要的是，它将通过提供更高的热稳定性，与苛刻的背面处理步骤的更大兼容性，通过封装保护晶片正面的凸块，在脱粘步骤中降低应力和减少剥离步骤来提高薄晶片处理解决方案的性能 正面的缺陷。

公开(公告)号：US20150064385A1

公开(公告)日：2015-03-05

申请号：US14472073

申请日：2014-08-28

Applicant: Brewer Science Inc.

Inventor： Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/683 ,  B32B38/08 ,  B32B38/00 ,  H01L21/306 ,  B32B38/10

CPC classification number: H01L21/6835 ,  B32B37/14 ,  B32B37/30 ,  B32B38/10 ,  B32B43/006 ,  B32B2037/243 ,  B32B2309/02 ,  B32B2309/04 ,  B32B2309/12 ,  B32B2457/14 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2221/68386 ,  Y10T156/11 ,  Y10T156/1168 ,  Y10T156/1179 ,  Y10T156/1195 ,  Y10T156/19 ,  Y10T156/1961 ,  Y10T156/1978 ,  Y10T156/1983 ,  Y10T156/1994 ,  Y10T428/1452 ,  Y10T428/31645 ,  Y10T428/31667 ,  Y10T428/31692

Abstract: A process is disclosed for using two polymeric bonding material layers to bond a device wafer and carrier wafer in a way that allows debonding to occur between the two layers under low-force conditions at room temperature. Optionally, a third layer is included at the interface between the two layers of polymeric bonding material to facilitate the debonding at this interface. This process can potentially improve bond line stability during backside processing of temporarily bonded wafers, simplify the preparation of bonded wafers by eliminating the need for specialized release layers, and reduce wafer cleaning time and chemical consumption after debonding.

Abstract translation: 公开了一种使用两个聚合物粘合材料层以在低温条件下在室温下在两层之间发生剥离的方式来接合器件晶片和载体晶片的方法。 可选地，第三层包含在两层聚合物粘合材料之间的界面处，以便于在该界面处脱粘。 该过程可以潜在地改善临时接合的晶片的背面处理期间的结合线稳定性，通过消除对专用隔离层的需要来简化接合晶片的制备，以及在脱粘后减少晶片清洗时间和化学消耗。

公开(公告)号：US09472436B2

公开(公告)日：2016-10-18

申请号：US14273369

申请日：2014-05-08

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/00 ,  H01L21/683 ,  H01L21/20 ,  H01L23/00 ,  B32B38/00 ,  B32B38/10 ,  B32B43/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

公开(公告)号：US20140239453A1

公开(公告)日：2014-08-28

申请号：US14273369

申请日：2014-05-08

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract translation: 提供临时连接半导体衬底的多个结合层方案。 在本发明的接合方案中，至少一个层直接与半导体衬底接触，且该方案中的至少两个层彼此直接接触。 本发明提供了多个处理选择，因为多层结构内的不同层执行特定的功能。 更重要的是，它将通过提供更高的热稳定性，与苛刻的背面处理步骤的更大兼容性，通过封装保护晶片正面的凸块，在脱粘步骤中降低应力和减少剥离步骤来提高薄晶片处理解决方案的性能 正面的缺陷。

公开(公告)号：US20140174627A1

公开(公告)日：2014-06-26

申请号：US14191544

申请日：2014-02-27

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L23/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

公开(公告)号：US20150122426A1

公开(公告)日：2015-05-07

申请号：US14550008

申请日：2014-11-21

Applicant: Brewer Science Inc.

Inventor： Rama Puligadda ,  Xing-Fu Zhong ,  Tony D. Flaim ,  Jeremy McCutcheon

IPC: H01L21/683 ,  B32B38/00 ,  B32B38/10 ,  B32B43/00

CPC classification number: H01L21/6835 ,  B32B38/0008 ,  B32B38/10 ,  B32B43/006 ,  H01L21/2007 ,  H01L21/6836 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/351 ,  Y10T156/10 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T428/24942 ,  Y10T428/26 ,  Y10T428/31511 ,  Y10T428/31551 ,  Y10T428/31663 ,  Y10T428/31721 ,  Y10T428/31725 ,  Y10T428/31935 ,  Y10T428/31938 ,  H01L2924/00

Abstract: Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.

Abstract translation: 提供临时连接半导体衬底的多个结合层方案。 在本发明的接合方案中，至少一个层直接与半导体衬底接触，且该方案中的至少两个层彼此直接接触。 本发明提供了多个处理选择，因为多层结构内的不同层执行特定的功能。 更重要的是，它将通过提供更高的热稳定性，与苛刻的背面处理步骤的更大兼容性，通过封装保护晶片正面的凸块，在脱粘步骤中降低应力和减少剥离步骤来提高薄晶片处理解决方案的性能 正面的缺陷。