公开(公告)号：US5973381A

公开(公告)日：1999-10-26

申请号：US508182

申请日：1995-07-27

申请人： Chiaki Kudo ,  Akihiro Yamamoto

发明人： Chiaki Kudo ,  Akihiro Yamamoto

IPC分类号： H01L21/225 ,  H01L21/334 ,  H01L27/06 ,  H01L27/08 ,  H01L29/94 ,  H01L29/00

CPC分类号： H01L29/66181 ,  H01L21/2253 ,  H01L27/0629 ,  H01L27/0805 ,  H01L29/94

摘要： A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silicon oxide layer. An impurity profile is formed in the region such that the concentration of the impurity increases from a surface common to the diffusion area and the silicon oxide layer towards the inside of the silicon substrate. The concentration of the impurity at the interface is less than or equal to 1.times.10.sup.20 cm.sup.-3, and a peak concentration lies at a depth of more than 0.05 .mu.m under the interface. This controls accelerated oxidization during the thermal oxidization and also controls the dependence of the capacitance on the voltage.

摘要翻译： MOS电容器具有p型硅衬底，通过将杂质注入到硅衬底的区域中形成的n型杂质扩散区，形成在扩散区上的氧化硅层和形成在氧化硅上的多晶硅电极 层。 在该区域中形成杂质分布，使得杂质的浓度从扩散区和硅氧化物层的共同表面朝向硅衬底的内部增加。 界面处的杂质浓度小于或等于1×1020cm-3，峰值浓度在界面下的深度大于0.05μm。 这控制了在热氧化期间的加速氧化，并且还控制电容对电压的依赖性。

公开(公告)号：US07863753B2

公开(公告)日：2011-01-04

申请号：US11896997

申请日：2007-09-07

申请人： Chiaki Kudo ,  Hisashi Ogawa

发明人： Chiaki Kudo ,  Hisashi Ogawa

IPC分类号： H01L29/41

CPC分类号： H01L29/42376 ,  H01L21/28123 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/0207 ,  H01L29/4238

摘要： A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

摘要翻译： 半导体器件包括：形成在半导体衬底中的隔离区; 由隔离区包围的有源区; 以及形成在所述隔离区域和所述有源区域上并且包括所述隔离区域上的第一区域的第一栅电极。 第一区域具有比有源区域上的第一栅电极的图案宽度大的栅极长度方向的图案宽度。 第一区域包括具有与活性区域上的第一栅电极的膜厚度不同的膜厚度的部分。

公开(公告)号：US07636494B2

公开(公告)日：2009-12-22

申请号：US11003735

申请日：2004-12-06

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： G06K9/40

CPC分类号： H04N5/372 ,  H04N5/3675 ,  H04N5/3728

摘要： When charges Q (x, y) transferred from an image inputting device 1 are to be converted into first signal intensities S′ (x, y) and signal processing is to be performed for the first signal intensity S′ (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S′ (x−1, y) and S′ (x+1, y) at adjacent pixels. When S′ (x, y)>Smax×A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save×C (where A and C are coefficients), whereas when S′ (x, y)

摘要翻译： 当从图像输入装置1传送的电荷Q（x，y）被转换为第一信号强度S'（x，y）时，对第一信号强度S'（x，y）进行信号处理 根据相邻像素处的信号强度S'（x-1，y）和S'（x + 1，y）计算特定像素，最大值Smax，最小值Smin和平均值Save。 当满足S'（x，y）> SmaxxA时，确定特定像素处的信号强度S（x，y）= SavexC（其中A和C是系数），而当S'（x，y） 确定信号强度S（x，y）= SavexD（其中B和D是系数），并且执行处理以获得适当的强度S（x，y）

公开(公告)号：US06346736B1

公开(公告)日：2002-02-12

申请号：US09469498

申请日：1999-12-22

申请人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

发明人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

IPC分类号： H01L3300

CPC分类号： H01L23/5222 ,  H01L21/76232 ,  H01L2924/0002 ,  H01L2924/00

摘要： The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. What results is a semiconductor device having lower total wiring-to-substrate capacitance and a higher operating speed.

摘要翻译： P型半导体衬底的顶表面被划分为有源区域，以形成元件和围绕有源区域的隔离区域。 隔离区域由沟槽部分和虚拟半导体部分组成。 在基板上沉积层间绝缘膜，然后在其上形成线。 在每个半导体部分中，与将离子注入到元件中同时形成杂质扩散层，使得在杂质扩散层和硅衬底之间形成PN结。 通过将杂质扩散层中的电容串联添加到层间绝缘膜中的电容而获得包含半导体部分的区域中的布线对基板电容的电容分量，该电容小于仅在中间层 绝缘膜。 具有较低的总布线对基板电容和更高的运行速度的半导体器件的结果是什么。

公开(公告)号：US20080073733A1

公开(公告)日：2008-03-27

申请号：US11819192

申请日：2007-06-26

申请人： Chiaki Kudo ,  Yoshihiro Sato

发明人： Chiaki Kudo ,  Yoshihiro Sato

IPC分类号： H01L21/3205 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/823443 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/4975 ,  H01L29/665

摘要： A semiconductor device includes a MIS transistor having a gate electrode which is fully silicided with metal. The edge parts of the gate electrode are lower in height than the other part thereof. Sidewall spacers are formed to cover the side and top surfaces of the edge parts of the gate electrode.

摘要翻译： 半导体器件包括具有完全用金属硅化的栅电极的MIS晶体管。 栅电极的边缘部分的高度低于其他部分。 形成侧壁间隔件以覆盖栅电极的边缘部分的侧表面和顶表面。

公开(公告)号：US20050048764A1

公开(公告)日：2005-03-03

申请号：US10923869

申请日：2004-08-24

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： G03F1/68 ,  G03F1/70 ,  G06F17/50 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522

CPC分类号： G06F17/5077 ,  Y10S438/942

摘要： In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

摘要翻译： 在互连掩模图案生成中，通过使用用于半导体器件等的单个最小线宽数据生成的互连图案，抑制了互连的可靠性的降低和制造成品率的降低。 当生成基于逻辑电路数据布置连接功能元件的互连的掩模上的布局布线图案时，基于最小线宽数据生成布线图形，基于最小线间距的互连图案 然后生成数据，并且生成在它们两者的中间布置新的互连边界的互连图案以用作最终互连图案，使得互连图案宽度变得适当地变宽，从而使得可以 提高互连的可靠性，抑制制造成品率的下降。

公开(公告)号：US6130139A

公开(公告)日：2000-10-10

申请号：US978137

申请日：1997-11-25

申请人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

发明人： Takaaki Ukeda ,  Chiaki Kudo ,  Toshiki Yabu

IPC分类号： H01L21/762 ,  H01L23/522 ,  H01L21/76

CPC分类号： H01L23/5222 ,  H01L21/76232 ,  H01L2924/0002

摘要： The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film. What results is a semiconductor device having lower total wiring to-substrate capacitance and a higher operating speed.

摘要翻译： P型半导体衬底的顶表面被划分为有源区域，以形成元件和围绕有源区域的隔离区域。 隔离区域由沟槽部分和虚拟半导体部分组成。 在基板上沉积层间绝缘膜，然后在其上形成线。 在每个半导体部分中，与将离子注入到元件中同时形成杂质扩散层，使得在杂质扩散层和硅衬底之间形成PN结。 通过将杂质扩散层中的电容串联添加到层间绝缘膜中的电容而获得包含半导体部分的区域中的布线对基板电容的电容分量，该电容仅小于相互之间的电容 层绝缘膜。 具有较低的总布线对衬底电容和较高工作速度的半导体器件的结果是什么。

公开(公告)号：US20080079088A1

公开(公告)日：2008-04-03

申请号：US11806878

申请日：2007-06-05

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823443 ,  H01L21/28097 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/4975

摘要： A semiconductor device includes an active region and a dummy active region formed in a semiconductor substrate to have a distance from each other, an isolation region formed between the active region and the dummy active region and has a top surface lower than top surfaces of the active region and the dummy active region, a gate insulating film formed on the active region and a fully silicided gate electrode formed on the isolation region, the gate insulating film and the dummy active region through full silicidation of a silicon gate material film with metallic material.

摘要翻译： 半导体器件包括形成在半导体衬底中的有源区和伪有源区，以形成彼此间隔的距离;形成在有源区和虚拟有源区之间的隔离区，并且具有比活性物体的顶表面低的顶表面 通过硅栅极材料膜与金属材料的全硅化，形成在有源区上形成的栅极绝缘膜和形成在隔离区上的完全硅化栅电极，栅极绝缘膜和虚设有源区。

公开(公告)号：US20070108530A1

公开(公告)日：2007-05-17

申请号：US11543223

申请日：2006-10-05

申请人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

发明人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864

摘要： A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on the sides of the gate electrode and an insulating film formed to cover the gate electrode and the source/drain regions to cause stress strain in part of the region below the gate electrode.

摘要翻译： 半导体器件包括形成在半导体区域的区域中的MIS晶体管。 MIS晶体管包括形成在该区域上的栅极绝缘膜，形成在栅极绝缘膜上并完全硅化金属的栅极电极，形成在栅极侧面上的部分区域中的源极/漏极区域和形成的绝缘膜 以覆盖栅极电极和源极/漏极区域，以在栅电极下方的部分区域引起应力应变。

公开(公告)号：US20070090417A1

公开(公告)日：2007-04-26

申请号：US11495662

申请日：2006-07-31

申请人： Chiaki Kudo

发明人： Chiaki Kudo

IPC分类号： H01L29/76

CPC分类号： H01L21/823864 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823835 ,  H01L21/82385 ,  H01L27/0629 ,  H01L29/4238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor device includes a first MIS transistor including a first gate electrode fully silicided with a metal. With the first MIS transistor includes: a first gate insulating film formed on a semiconductor region; the first gate electrode formed on the first gate insulating film; a first sidewall spacer formed on a side of the first gate electrode; and a second sidewall spacer formed at the side of the first gate electrode with the first sidewall spacer interposed therebetween; the first sidewall spacer and the second sidewall spacer have different etching characteristics. The first sidewall spacer has an upper end lower than an upper surface of the first gate electrode and an upper end of the second sidewall spacer.

摘要翻译： 半导体器件包括第一MIS晶体管，其包括完全用金属硅化的第一栅电极。 利用第一MIS晶体管包括：形成在半导体区域上的第一栅极绝缘膜; 形成在第一栅极绝缘膜上的第一栅电极; 形成在所述第一栅电极的一侧上的第一侧壁间隔物; 以及形成在所述第一栅电极的侧面处的第二侧壁间隔件，其间插入有所述第一侧壁间隔物; 第一侧壁间隔件和第二侧壁间隔件具有不同的蚀刻特性。 第一侧壁间隔件的上端低于第一栅电极的上表面和第二侧壁间隔件的上端。