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    Semiconductor device and method for manufacturing the same
    2.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08004044B2

    公开(公告)日：2011-08-23

    申请号：US12473710

    申请日：2009-05-28

    申请人： Hisashi Ogawa ,  Yoshihiro Mori

    发明人： Hisashi Ogawa ,  Yoshihiro Mori

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor device including a first transistor of a first conductivity type provided on a first active region of a semiconductor region, and a second transistor of a second conductivity type provided on a second active region of the semiconductor region. The first transistor includes a first gate insulating film and a first gate electrode, the first gate insulating film contains a high-k material and a first metal, and the first gate electrode includes a lower conductive film, a first conductive film and a first silicon film. The second transistor includes a second gate insulating film and a second gate electrode, the second gate insulating film contains a high-k material and a second metal, and the second gate electrode includes a second conductive film made of the same material as the first conductive film, and a second silicon film.

    摘要翻译： 一种半导体器件，包括设置在半导体区域的第一有源区上的第一导电类型的第一晶体管和设置在半导体区域的第二有源区上的第二导电类型的第二晶体管。 第一晶体管包括第一栅极绝缘膜和第一栅电极，第一栅极绝缘膜包含高k材料和第一金属，并且第一栅电极包括下导电膜，第一导电膜和第一硅 电影。 第二晶体管包括第二栅极绝缘膜和第二栅电极，第二栅极绝缘膜包含高k材料和第二金属，第二栅极包括由与第一导电性材料相同的材料制成的第二导电膜 膜和第二硅膜。

    Semiconductor device and fabrication method for the same
    3.
    发明授权
    Semiconductor device and fabrication method for the same 有权
    半导体器件及其制造方法相同

    公开(公告)号：US07977800B2

    公开(公告)日：2011-07-12

    申请号：US12247518

    申请日：2008-10-08

    申请人： Tsutomu Oosuka ,  Hisashi Ogawa ,  Yoshihiro Sato

    发明人： Tsutomu Oosuka ,  Hisashi Ogawa ,  Yoshihiro Sato

    IPC分类号： H01L21/8234

    CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/11 ,  H01L29/161 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in portions of the semiconductor substrate on both sides of the gate electrode; a gate interconnect formed at a position opposite to the gate electrode with respect to the first source/drain region; and a first silicon-germanium layer formed on the first source/drain region to protrude above the top surface of the semiconductor substrate. The gate interconnect and the first source/drain region are connected via a local interconnect structure that includes the first silicon-germanium layer.

    摘要翻译： 半导体器件包括：晶体管，其具有形成在半导体衬底上的栅极电极和形成在半导体衬底的位于栅电极两侧的部分中的第一和第二源极/漏极区域; 形成在相对于第一源极/漏极区域的与栅电极相对的位置处的栅极互连; 以及形成在所述第一源极/漏极区域上以在所述半导体衬底的顶表面上方突出的第一硅 - 锗层。 栅极互连和第一源极/漏极区域经由包括第一硅 - 锗层的局部互连结构连接。

    Semiconductor device and method for manufacturing the same
    4.
    发明申请
    Semiconductor device and method for manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20070108530A1

    公开(公告)日：2007-05-17

    申请号：US11543223

    申请日：2006-10-05

    申请人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

    发明人： Hisashi Ogawa ,  Yasushi Naito ,  Chiaki Kudo

    IPC分类号： H01L29/94 ,  H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/823864

    摘要： A semiconductor device includes a MIS transistor formed in a region of a semiconductor region. The MIS transistor includes a gate insulating film formed on the region, a gate electrode formed on the gate insulating film and fully silicided with metal, source/drain regions formed in parts of the region on the sides of the gate electrode and an insulating film formed to cover the gate electrode and the source/drain regions to cause stress strain in part of the region below the gate electrode.

    摘要翻译： 半导体器件包括形成在半导体区域的区域中的MIS晶体管。 MIS晶体管包括形成在该区域上的栅极绝缘膜，形成在栅极绝缘膜上并完全硅化金属的栅极电极，形成在栅极侧面上的部分区域中的源极/漏极区域和形成的绝缘膜 以覆盖栅极电极和源极/漏极区域，以在栅电极下方的部分区域引起应力应变。

    Semiconductor device and its manufacturing method
    5.
    发明授权
    Semiconductor device and its manufacturing method 有权
    半导体器件及其制造方法

    公开(公告)号：US06995415B2

    公开(公告)日：2006-02-07

    申请号：US10475115

    申请日：2003-02-14

    申请人： Hisashi Ogawa ,  Hiroaki Nakaoka ,  Atsuhiro Kajiya ,  Shin Hashimoto ,  Kyoko Egashira

    发明人： Hisashi Ogawa ,  Hiroaki Nakaoka ,  Atsuhiro Kajiya ,  Shin Hashimoto ,  Kyoko Egashira

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10852 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897

    摘要： A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

    摘要翻译： 存储单元晶体管和平面电容器设置在存储区域中，CMOS器件的两个晶体管都设置在逻辑电路区域中。 平面电容器的电容电介质15和平板电极16b设置在与浅沟槽隔离层12a共同的沟槽上，并且沟槽的上部填充有电容电介质15和板电极16b。 形成作为存储节点的n型扩散层19，其端部区域沿着沟槽的上部的一侧延伸到与浅沟槽隔离层12a重叠的区域。 可以增加用作电容器的基板的一部分的面积，而不增加基板面积。

    Semiconductor device and associated fabrication method
    8.
    发明授权
    Semiconductor device and associated fabrication method 失效
    半导体器件及相关制造方法

    公开(公告)号：US5786273A

    公开(公告)日：1998-07-28

    申请号：US602575

    申请日：1996-02-14

    申请人： Toshitaka Hibi ,  Takatoshi Yasui ,  Hisashi Ogawa ,  Susumu Akamatsu ,  Shunsuke Kugo

    发明人： Toshitaka Hibi ,  Takatoshi Yasui ,  Hisashi Ogawa ,  Susumu Akamatsu ,  Shunsuke Kugo

    IPC分类号： H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/768

    摘要： Formed in a second interlayer dielectric are a first contact hole and a second contact hole. The first and second contact holes each extend to a first-level interconnect line. Tungsten is formed on the entirety of a substrate to form a first plug, a second plug, and a tungsten layer. A silicon oxide layer is formed. Thereafter, a patterning process is carried out to form a second-level interconnect line which is connected with the first plug and a top protective layer, and the top of the second plug remains exposed. A sidewall is formed on the side surfaces of the second-level interconnect line and the top protective layer. Subsequently, a third-level interconnect line, which is connected with the exposed second plug, is formed. Such arrangement not only reduces the number of contact hole formation masks, it also cuts down the number of fabrication steps. Further, the aspect ratio of the second contact hole becomes lower thereby achieving highly reliable semiconductor devices.

    摘要翻译： 形成在第二层间电介质中的是第一接触孔和第二接触孔。 第一和第二接触孔各自延伸到第一级互连线。 在整个基板上形成钨以形成第一插塞，第二插头和钨层。 形成氧化硅层。 此后，进行图案化处理以形成与第一插头和顶部保护层连接的第二级互连线，并且第二插头的顶部保持暴露。 侧壁形成在第二级互连线和顶部保护层的侧表面上。 随后，形成与暴露的第二插头连接的第三级互连线。 这种布置不仅减少了接触孔形成掩模的数量，而且还减少了制造步骤的数量。 此外，第二接触孔的纵横比变低，从而实现高可靠性的半导体器件。

    Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level
    10.
    发明授权
    Semiconductor memory device in which a capacitor electrode of a memory cell and an interconnection layer of a peripheral circuit are formed in one level 失效
    半导体存储器件，其中存储单元的电容器电极和外围电路的互连层形成在一个级中

    公开(公告)号：US5399890A

    公开(公告)日：1995-03-21

    申请号：US257955

    申请日：1994-06-10

    申请人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

    发明人： Shozo Okada ,  Hisashi Ogawa ,  Naoto Matsuo ,  Yoshiro Nakata ,  Toshiki Yabu ,  Susumu Matsumoto

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/105 ,  H01L27/10808

    摘要： A semiconductor memory of the invention includes a semiconductor substrate having a plurality of transistors, a plurality of stacked capacitors connected to portions of the plurality of transistors, a plurality of first level interconnection layers connected to other portions of the plurality of transistors, and a plurality of second level interconnection layers disposed above the stacked capacitors and the first level interconnection layers. Each of the plurality of stacked capacitors includes a first electrode layer, a capacitance insulating film formed on top of the first electrode layer, and a second electrode layer formed on top of the capacitance insulating film. The second electrode layer is connected to a portion of one of the plurality of second level interconnection layers. At least portions of the plurality of first level interconnection layers are connected to other portions of the plurality of second level interconnection layers. Each of the plurality of first level interconnection layers shares the same layer as at least one of the first electrode layer and the second electrode layer.

    摘要翻译： 本发明的半导体存储器包括具有多个晶体管的半导体衬底，与多个晶体管的一部分连接的多个叠层电容器，与多个晶体管的其它部分连接的多个第一级互连层，以及多个晶体管的多个 位于层叠电容器和第一级互连层之上的第二级互连层。 多个叠层电容器中的每一个包括第一电极层，形成在第一电极层顶部的电容绝缘膜，以及形成在电容绝缘膜顶部的第二电极层。 第二电极层连接到多个第二级互连层之一的一部分。 多个第一级互连层的至少一部分连接到多个第二级互连层的其它部分。 多个第一级互连层中的每一个与第一电极层和第二电极层中的至少一个共享相同的层。