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5 条记录 (耗时 0.037 秒)

    CMOS to GPI interface circuit
    4.
    发明授权
    CMOS to GPI interface circuit 失效
    CMOS到GPI接口电路

    公开(公告)号：US4866308A

    公开(公告)日：1989-09-12

    申请号：US179699

    申请日：1988-04-11

    申请人： Delbert R. Cecchi ,  Hyung S. Kim ,  John S. Mitby ,  David P. Swart ,  Balsha R. Stanisic ,  Philip T. Wu

    发明人： Delbert R. Cecchi ,  Hyung S. Kim ,  John S. Mitby ,  David P. Swart ,  Balsha R. Stanisic ,  Philip T. Wu

    IPC分类号： H03K5/02 ,  H03K19/003 ,  H03K19/0185

    CPC分类号： H03K19/018521 ,  H03K19/00361

    摘要： A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines. The feedback circuitry uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry that discharges the voltage level of the feedback circuitry when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.

    Fiber optic transceiver array and fiber optic transceiver channel for short wave fiber optic communications
    5.
    发明授权
    Fiber optic transceiver array and fiber optic transceiver channel for short wave fiber optic communications 失效

    公开(公告)号：US07076178B2

    公开(公告)日：2006-07-11

    申请号：US11137278

    申请日：2005-05-25

    申请人： Randolph B. Heineke ,  David J. Orser ,  David P. Swart

    发明人： Randolph B. Heineke ,  David J. Orser ,  David P. Swart

    IPC分类号： H04B10/156

    CPC分类号： G01M11/30 ,  G02B6/4249

    摘要： A fiber optic transceiver array and a fiber optic transceiver channel are provided for short wave fiber optic communications. A fiber optic transceiver array for short wave fiber optic communications includes a series of fiber optic transceiver channels. Each fiber optic transceiver channel includes a plurality of test pads. A power distribution bypass capacitor is distributed along the series of fiber optic transceiver channels. A plurality of high voltage power supply and ground connections are coupled through the power distribution bypass capacitor and distributed around the series of fiber optic transceiver channels. A threaded high voltage power supply connection is provided to alternating ones of the series of fiber optic transceiver channels. A threaded ground connection is provided to alternating other ones of the series of fiber optic transceiver channels to reduce power noise generation and susceptibility to noise between adjacent channels. A power to ground decoupling capacitor included with each fiber optic transceiver channel also enhances power noise sensitivity reduction. A fiber optic transceiver channel for short wave fiber optic communications includes at least a high voltage power supply connection and a ground connection. A plurality of test pads includes at least a ground connection and a pair of differential output connections. A channel decoupling capacitor is positioned proximate to the pair of differential output connections.