公开(公告)号：US20170374456A1

公开(公告)日：2017-12-28

申请号：US15195626

申请日：2016-06-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Tejasvi DAS ,  Anand ILANGO

IPC: H04R3/00 ,  H03F3/181 ,  H03F3/20

CPC classification number: H04R3/007 ,  H03F1/305 ,  H03F1/34 ,  H03F3/181 ,  H03F3/187 ,  H03F3/20 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/129 ,  H03F2200/381 ,  H03F2200/408 ,  H03G3/348 ,  H03M1/66

Abstract: A method may be provided for powering up or down a playback path comprising a digital-to-analog converter (DAC) for generating a non-ground-centered analog intermediate voltage centered at a common-mode voltage and coupled to a driver for generating a ground-centered playback path output voltage at an output of the driver wherein the output of the driver is clamped via a finite impedance to a ground voltage. The method may include transitioning continuously or in a plurality of discrete steps the analog intermediate voltage from an initial voltage to the common-mode voltage such that the transitioning is substantially inaudible at the output of the driver. A method for operating an output clamp of an output driver stage of a playback path may include transitioning continuously or in a plurality of discrete steps an impedance of the output clamp in order to match an output offset of the output driver stage in order to minimize audio artifacts appearing at an output of the output driver stage.

公开(公告)号：US20230144960A1

公开(公告)日：2023-05-11

申请号：US17846832

申请日：2022-06-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Anand ILANGO ,  Siddharth MARU ,  Tejasvi DAS ,  John L. MELANSON

IPC: G01R27/16 ,  H03F3/04

CPC classification number: G01R27/16 ,  H03F3/04

Abstract: A system may include amplifier circuitry configured to drive an electromagnetic load with a driving signal and a processing system communicatively coupled to the electromagnetic load and configured to compensate for current-sensing error of the processing system caused by feedback circuitry of the amplifier circuitry.

公开(公告)号：US20210344310A1

公开(公告)日：2021-11-04

申请号：US17003564

申请日：2020-08-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ramin ZANBAGHI ,  Cory J. PETERSON ,  Anand ILANGO ,  Eric KIMBALL

IPC: H03F3/217 ,  H03F3/45 ,  G05F1/46 ,  H03F1/38 ,  G01R1/20 ,  G01R19/175 ,  G01R19/165 ,  H04R1/10

Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.

公开(公告)号：US20210344309A1

公开(公告)日：2021-11-04

申请号：US16864893

申请日：2020-05-01

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Ramin ZANBAGHI ,  Cory J. PETERSON ,  Anand ILANGO ,  Eric KIMBALL

IPC: H03F3/217

Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first low-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second low-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.