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公开(公告)号：US20230006612A1
公开(公告)日：2023-01-05
申请号：US17940332
申请日：2022-09-08
Inventor： Chandra PRAKASH , Cory J. PETERSON , Eric KIMBALL
Abstract: An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.
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公开(公告)号：US20230003779A1
公开(公告)日：2023-01-05
申请号：US17668445
申请日：2022-02-10
Inventor： Saurabh SINGH , Chandra B. PRAKASH , Eric KIMBALL , Cory J. PETERSON , Ryan LOBO
IPC: G01R27/08
Abstract: A method for estimating resistances of a circuit having a plurality of resistances comprising a first resistance and a second resistance may include applying a first bias voltage across the circuit and measuring a first voltage at a common node between the first resistance and the second resistance in order to determine a mathematical relationship between the first resistance and the second resistance, applying a second bias voltage across the circuit and a third resistance in parallel with the circuit and measuring a second voltage at the common node between the first resistance and the second resistance in order to determine a mathematical relationship between the third resistance and at least one of the first resistance and the second resistance, and based on at least the measurement of the first voltage and the measurement of the second voltage, determining the first resistance and the second resistance as a function of the third resistance.
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公开(公告)号：US20210297072A1
公开(公告)日：2021-09-23
申请号：US16820897
申请日：2020-03-17
Inventor： Ramin ZANBAGHI , Cory J. PETERSON
IPC: H03K17/081 , H03K7/08
Abstract: A system may include an output driving stage comprising a first switch configured to selectively open and close an electrical path between a first supply voltage and an output terminal of the output driving stage and a second switch configured to selectively open and close an electrical path between a second supply voltage and the output terminal of the output driving stage, wherein the second supply voltage is lower than the first supply voltage. The system may also include detection and protection circuitry configured to monitor a physical quantity indicative of the second supply voltage and responsive to the physical quantity exceeding an overvoltage threshold, electrically isolate the output terminal from the second supply voltage.
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公开(公告)号：US20230146592A1
公开(公告)日：2023-05-11
申请号：US17729626
申请日：2022-04-26
Inventor： Chandra B. PRAKASH , Tejasvi DAS , Cory J. PETERSON , Siddharth MARU
CPC classification number: H03F3/2173 , H03F3/213 , H03M1/12
Abstract: Circuitry for driving a load, the circuitry comprising: driver circuitry; and load sensing circuitry, wherein the circuitry is operable in: a driving mode of operation in which the driver circuitry supplies a drive signal to a load coupled to the circuitry; and a load sensing mode of operation, for estimating a characteristic of a load coupled to the circuitry based on a signal output by the load sensing circuitry in response to a stimulus signal, wherein the circuitry is configured to, in response to a request for operation of the circuitry in the load sensing mode: compare an indication of a current through the load to a predefined threshold; and if the indication of the current through the load meets the predefined threshold, prevent or delay operation in the load sensing mode.
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5.发明申请公开(公告)号：US20210351751A1
公开(公告)日：2021-11-11
申请号：US16869226
申请日：2020-05-07
Inventor： Ramin ZANBAGHI , Cory J. PETERSON , Eric KIMBALL
Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a sense resistor, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the sense resistor. The system may additionally include a modulator for generating a differential pulse-width modulation driving signal to the first high-side switch, the second high-side switch, the first low-side switch, and the second low-side switch and pilot tone injection circuitry configured to inject a periodic pilot tone into the differential pulse-width modulation driving signal at a pilot tone frequency.
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Patent Agency Ranking
公开(公告)号：US20230141666A1
公开(公告)日：2023-05-11
申请号：US17545378
申请日：2021-12-08
Inventor： Chandra B. PRAKASH , Cory J. PETERSON
IPC: G11C7/10
CPC classification number: G11C7/1057 , H03K19/00361
Abstract: In accordance with embodiments of the present disclosure, a system may include a driver configured to drive a load with a single-ended driving signal and a signal return path for the load, wherein the signal return path comprises a voltage-mode driver configured to create a signal offset during an idle channel mode of the system in order to minimize idle channel noise at the load.
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公开(公告)号：US20210344310A1
公开(公告)日：2021-11-04
申请号：US17003564
申请日：2020-08-26
Inventor： Ramin ZANBAGHI , Cory J. PETERSON , Anand ILANGO , Eric KIMBALL
IPC: H03F3/217 , H03F3/45 , G05F1/46 , H03F1/38 , G01R1/20 , G01R19/175 , G01R19/165 , H04R1/10
Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first high-side switch and the supply voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first high-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second high-side switch and the supply voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second high-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.
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公开(公告)号：US20210344309A1
公开(公告)日：2021-11-04
申请号：US16864893
申请日：2020-05-01
Inventor： Ramin ZANBAGHI , Cory J. PETERSON , Anand ILANGO , Eric KIMBALL
IPC: H03F3/217
Abstract: A system may include a Class-D stage comprising a first high-side switch coupled between a supply voltage and a first output terminal of the Class-D stage, a second high-side switch coupled between the supply voltage and a second output terminal of the Class-D stage, a first low-side switch coupled between a ground voltage and the first output terminal, and a second low-side switch coupled between the ground voltage and the second output terminal. The system may also include current sensing circuitry comprising a first sense resistor coupled between the first low-side switch and the ground voltage, such that an output current through a load coupled between the first output terminal and the second output terminal causes a first sense voltage proportional to the output current across the first sense resistor when the first low-side switch is activated. The current sensing circuitry may also include a second sense resistor coupled between the second low-side switch and the ground voltage, such that an output current through the load causes a second sense voltage proportional to the output current across the second sense resistor when the second low-side switch is activated. The system may also include measurement circuitry configured to measure the first sense voltage and the second sense voltage to determine the output current.
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公开(公告)号：US20240168506A1
公开(公告)日：2024-05-23
申请号：US18280859
申请日：2022-03-14
Inventor： Tejasvi DAS , Siddharth MARU , Cory J. PETERSON , John L. MELANSON
CPC classification number: G05F1/56 , G01R19/0092 , G01R27/16
Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises: primary driver circuitry coupled to a primary signal path and operable to drive the load with a playback signal in a first mode of operation of the circuitry, wherein a playback signal comprises a signal that drives the load to generate a desired output; auxiliary driver circuitry coupled to an auxiliary signal path; an auxiliary current sense resistor in the auxiliary signal path; and current detection circuitry coupled to the auxiliary current sense resistor and configured to generate a signal indicative of a current through the load. One of the primary driver circuitry and the auxiliary driver circuitry is operable to drive the load with a pilot signal in a second mode of operation of the circuitry, wherein a pilot signal comprises a signal having a predefined frequency or frequency content and a predefined magnitude.
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公开(公告)号：US20220357757A1
公开(公告)日：2022-11-10
申请号：US17508204
申请日：2021-10-22
Inventor： Tejasvi DAS , Siddharth MARU , Cory J. PETERSON
Abstract: The present disclosure relates to circuitry for driving a load. The circuitry comprises: primary driver circuitry coupled to a primary signal path and operable to drive the load with a playback signal in a first mode of operation of the circuitry, wherein a playback signal comprises a signal that drives the load to generate a desired output; auxiliary driver circuitry coupled to an auxiliary signal path; an auxiliary current sense resistor in the auxiliary signal path; and current detection circuitry coupled to the auxiliary current sense resistor and configured to generate a signal indicative of a current through the load. One of the primary driver circuitry and the auxiliary driver circuitry is operable to drive the load with a pilot signal in a second mode of operation of the circuitry, wherein a pilot signal comprises a signal having a predefined frequency or frequency content and a predefined magnitude.
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