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Patent Agency Ranking
公开(公告)号：US20160126971A1
公开(公告)日：2016-05-05
申请号：US14991467
申请日：2016-01-08
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse
Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
Abstract translation: 在一个实现中，数字模拟转换器（DAC）是单调的，因为输出仅在输入的方向上移动并被分段，因为DAC的更重要部分与较不重要的部分分离。 DAC接收包含多个最高有效位和多个最低有效位的输入二进制字。 DAC将输入二进制字解码为包括等于或大于二进制字的位宽的位宽的中间信号。 中间信号设置输出开关和电流源开关。 DAC提供表示输入二进制字的模拟输出信号。
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公开(公告)号：US09397687B2
公开(公告)日：2016-07-19
申请号：US14991467
申请日：2016-01-08
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse
Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
Abstract translation: 在一个实现中，数字模拟转换器（DAC）是单调的，因为输出仅在输入的方向上移动并被分段，因为DAC的更重要部分与较不重要的部分分离。 DAC接收包含多个最高有效位和多个最低有效位的输入二进制字。 DAC将输入二进制字解码为包括等于或大于二进制字的位宽的位宽的中间信号。 中间信号设置输出开关和电流源开关。 DAC提供表示输入二进制字的模拟输出信号。
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公开(公告)号：US09258010B1
公开(公告)日：2016-02-09
申请号：US14473340
申请日：2014-08-29
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse
Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
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公开(公告)号：US09793902B2
公开(公告)日：2017-10-17
申请号：US15048040
申请日：2016-02-19
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse , Bibhu Das , Bipin Dama
CPC classification number: H03L7/0807 , H03L7/087 , H03L7/093 , H03L7/095 , H03L7/113 , H04L7/0004 , H04L7/033 , H04L7/0331
Abstract: Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.
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公开(公告)号：US20160065234A1
公开(公告)日：2016-03-03
申请号：US14473340
申请日：2014-08-29
Applicant: Cisco Technology, Inc.
Inventor： Kadaba Lakshmikumar , Mark Y. Tse
IPC: H03M1/68
Abstract: In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
Abstract translation: 在一个实现中，数字模拟转换器（DAC）是单调的，因为输出仅在输入的方向上移动并被分段，因为DAC的更重要部分与较不重要的部分分离。 DAC接收包含多个最高有效位和多个最低有效位的输入二进制字。 DAC将输入二进制字解码为包括等于或大于二进制字的位宽的位宽的中间信号。 中间信号设置输出开关和电流源开关。 DAC提供表示输入二进制字的模拟输出信号。
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