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公开(公告)号：US07023941B1
公开(公告)日：2006-04-04
申请号：US10384585
申请日：2003-03-11
申请人： Claudio Gustavo Rey , Jonathan Robert Gay , William Michael Lye , Ognjen Katic , Terence K. W. Lau , Jatinder Singh Chana
发明人： Claudio Gustavo Rey , Jonathan Robert Gay , William Michael Lye , Ognjen Katic , Terence K. W. Lau , Jatinder Singh Chana
IPC分类号： H04L7/00
CPC分类号： H04L7/0058 , H04L2025/03471
摘要： An apparatus and method for jointly equalizing a return to zero (RZ) signal and detecting timing errors in the RZ signal, using values or indices from equalizer taps, including a set reference tap that does not shift. A timing error detector detects a timing error based on a group delay measured from the equalizer tap information, and then adjustment circuitry modifies samples of the received RZ signal prior to their equalization to offset that timing error. Methods of modifying the samples to offset the timing error include adjusting the timing of the sampler, or adjusting the sampled data using intermediate, interpolated samples generated by a timing interpolation filter.
摘要翻译： 使用来自均衡器抽头的值或索引（包括不移位的设定参考点击）来共同平衡返回零（RZ）信号和检测RZ信号中的定时误差的装置和方法。 定时误差检测器基于从均衡器抽头信息测量的组延迟来检测定时误差，然后调整电路在其均衡之前修改所接收的RZ信号的采样以偏移该定时误差。 修改样本以偏移定时误差的方法包括调整采样器的定时，或者使用由定时内插滤波器生成的中间插值采样来调整采样数据。
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公开(公告)号：US07154946B1
公开(公告)日：2006-12-26
申请号：US10618017
申请日：2003-07-14
申请人： Ognjen Katic , Claudio Gustavo Rey
发明人： Ognjen Katic , Claudio Gustavo Rey
CPC分类号： H04L7/0058 , H04L25/03038 , H04L2025/03356
摘要： An equalizer for return-to-zero (RZ) signals comprises: (a) an equalizer core for equalizing the received signal; (b) a decision corrector for detecting and correcting misplaced pulses and double pulses in the equalized signal using known characteristics and properties of the RZ signal itself; and (c) an error calculator that generates an error signal for updating tap values based on the initial outputs of the equalizer core and the corrected outputs of the decision corrector. The decision corrector comprises a zero assertion counter that generates a clock synchronized with the timing of the received signal, and corrects the equalized signal by forcing zeroes in those portions of the equalized signal that the synchronized clock indicates should be “RZ” zeroes (as opposed to “data” zeroes or “data” symbols “1” or “−1”). The decision corrector further comprises a misplaced pulse detector for detecting misplaced pulses and double pulses based on both the output of the zero assertion counter and coding in the RZ signal, and corrects the equalized signal by moving the misplaced pulse or doubled portion of the pulse forward or backward in time in accordance with the principles of the RZ coding scheme used. The equalizer can further comprise interpolators for generating a plurality of signals based on the equalized signal, to provide a greater diversity of information for the decision corrector.
摘要翻译： 用于归零（RZ）信号的均衡器包括：（a）用于均衡接收信号的均衡器核; （b）用于使用RZ信号本身的已知特性和性质来检测和校正均衡信号中的错位脉冲和双脉冲的判定校正器; 以及（c）误差计算器，其基于均衡器核的初始输出和判定校正器的校正输出产生用于更新抽头值的误差信号。 该判定校正器包括一个产生与接收信号的定时同步的时钟的零置位计数器，并且通过在均衡信号的那些部分中强制零来纠正均衡信号，同步时钟指示应该是“RZ”为零 到“数据”零或“数据”符号“1”或“-1”）。 判决校正器还包括一个错位脉冲检测器，用于根据零置信计数器的输出和RZ信号中的编码来检测错位脉冲和双脉冲，并通过将错位的脉冲或双倍部分向前移动来校正均衡信号 或者按照所使用的RZ编码方案的原理在时间上落后。 均衡器还可以包括用于基于均衡信号产生多个信号的内插器，以为决策校正器提供更多的信息分集。
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公开(公告)号：US06269131B1
公开(公告)日：2001-07-31
申请号：US09086974
申请日：1998-05-28
IPC分类号： H04B1500
CPC分类号： H04L25/023 , H04L25/025
摘要： A physical channel estimator for a communication system using pilot symbols and an equalizer uses a model of the system in which the impulse response of the physical channel is considered separately from the impulse responses of the pulse shaping filters in the transmitter and receiver of the communication system. The system is modeled as if the signals were propagated first through both pulse shaping filters and then through the physical channel. To estimate the physical channel impulse response, known pilot symbols are transmitted and then sampled. The pilot symbol samples and the known impulse responses of the pulse shaping filters are then used to estimate the physical channel impulse response. In one embodiment, the physical channel impulse response is considered time-invariant over the estimation period and a sufficient number of pilot symbol samples are taken so that the system is overdetermined. A least squares method is then used to estimate the physical channel impulse response from the pilot symbol samples and the known responses of the pulse shaping filters. Further refinements include conditioning the estimated physical channel impulse response to improve performance in low SNR conditions and estimating a DC offset incurred from demodulating the received signal.
摘要翻译： 用于使用导频符号和均衡器的通信系统的物理信道估计器使用系统的模型，其中物理信道的脉冲响应与通信系统的发射机和接收机中的脉冲整形滤波器的脉冲响应分开考虑 。 该系统被建模为首先通过两个脉冲整形滤波器然后通过物理信道传播信号。 为了估计物理信道脉冲响应，发送已知的导频符号然后采样。 然后使用导频符号采样和脉冲整形滤波器的已知脉冲响应来估计物理信道脉冲响应。 在一个实施例中，物理信道脉冲响应在估计周期内被认为是时间不变的，并且采用足够数量的导频符号样本，使得系统被过度确定。 然后使用最小二乘法来估计来自导频符号样本的物理信道脉冲响应和脉冲整形滤波器的已知响应。 进一步的改进包括调整估计的物理信道脉冲响应以改善低SNR条件下的性能并且估计从解调接收到的信号引起的DC偏移。
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4.发明授权Cascaded jitter frequency shifting Δ-Σ modulated signal synchronization mapper 有权级联抖动频移Delta-Sigma调制信号同步映射器公开(公告)号：US07298808B1
公开(公告)日：2007-11-20
申请号：US10424718
申请日：2003-04-29
申请人： Claudio Gustavo Rey
发明人： Claudio Gustavo Rey
摘要： The invention provides a synchronizer incorporating a Δ-Σ modulator (i.e. a bit stuffing command generator), coupled in series with a frequency offset measurement block and a frequency-locked loop, to synchronize the data rate of an output data stream to that of an input data stream such that jitter energy is shifted up in frequency, simplifying attenuation of the jitter energy when the output data stream is desynchronized (demapped). Placement of the Δ-Σ modulator outside the frequency-locked loop allows selectable adjustment of the frequency offset measurement block's frequency. A mapper incorporating the Δ-Σ modulator interprets the pulse train output by the Δ-Σ modulator as stuff/null/de-stuff commands.
摘要翻译： 本发明提供了一种同步器，其包括与偏移测量块和频率锁相环串联耦合的Δ-Σ调制器（即，位填充命令发生器），以将输出数据流的数据速率与 输入数据流，使得抖动能量在频率上向上移位，从而简化当输出数据流不同步（去映射）时抖动能量的衰减。 频率锁定环路之外的Delta-Sigma调制器的放置允许选择性地调整频偏测量块的频率。 结合Delta-Sigma调制器的映射器将Delta-Sigma调制器的脉冲串输出解释为填充/空/解除命令。
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5.发明授权
公开(公告)号：US5923712A
公开(公告)日：1999-07-13
申请号：US850940
申请日：1997-05-05
申请人： Robert Richard Leyendecker , Jay Jui-Chieh Chen , Armando Cova Garrido , Yan Guo , Vladimir Pavlovic , Claudio Gustavo Rey , Desmond Wai Ming Yan
发明人： Robert Richard Leyendecker , Jay Jui-Chieh Chen , Armando Cova Garrido , Yan Guo , Vladimir Pavlovic , Claudio Gustavo Rey , Desmond Wai Ming Yan
CPC分类号： H03F1/3247 , H03F2201/3224 , H03F2201/3233
摘要： A system for linearly transmitting an amplified output signal using predistortion whereby a straight inverse modeling scheme is used to more easily and accurately determine the inverse of the distortion caused by a power amplifier of a RF transmitter. The "inverse" of the power amplifier is directly modeled by considering the power amplifier as a signal processing block with the input and output ports reversed. As a result, the computationally intensive inversion required by conventional schemes is avoided. The predistorter system stores complex coefficients in a predistorter LUT, which are then used as the tap weights of a digital filter implementing the predistorter. The predistortion is done by a non-linear filter which incorporates both instantaneous and average envelope power or magnitude effects. The predistortion LUT is addressed as a function of the instantaneous envelope power or magnitude and past power or magnitude envelopes. This scheme takes into account the instantaneous envelope power or magnitude of the current sample and a profile of the envelope power or magnitude of previous samples to accurately compensate for modulation envelope memory effects of the power amplifier. The past powers or magnitudes provide an indication of the trajectory of the power or magnitude leading to the current power or magnitude, which enables the predistorter to more accurately compensate for the power amplifier distortion. The predistorter LUT is updated with values that are indexed as a function of the powers or magnitudes of past samples and the power or magnitude of the current sample.
摘要翻译： 一种用于使用预失真线性地传输放大的输出信号的系统，由此使用直的逆建模方案来更容易且准确地确定由RF发射机的功率放大器引起的失真的倒数。 通过考虑功率放大器作为输入和输出端口反转的信号处理块，直接建模功率放大器的“反向”。 结果，避免了常规方案所需的计算密集型反转。 预失真器系统将复数系数存储在预失真器LUT中，然后将其用作实现预失真器的数字滤波器的抽头权重。 预失真由非线性滤波器完成，其包含瞬时和平均包络功率或幅度效应。 预失真LUT作为瞬时包络功率或幅度以及过去功率或幅度包络的函数来寻址。 该方案考虑了当前采样的瞬时包络功率或幅度以及前一采样的包络功率或幅度的曲线，以准确地补偿功率放大器的调制包络存储器效应。 过去的功率或幅度提供了导致当前功率或幅度的功率或幅度的轨迹的指示，这使得预失真器能够更准确地补偿功率放大器失真。 预失真器LUT被更新为按照过去采样的功率或幅度以及当前采样的功率或幅度进行索引的值。
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公开(公告)号：US06173011B2
公开(公告)日：2001-01-09
申请号：US09086205
申请日：1998-05-28
IPC分类号： H03H730
CPC分类号： H03H17/0461 , H03H17/0288 , H03H17/0416 , H04L25/0232 , H04L2025/0349
摘要： An interpolator having a linear phase response has a first stage implemented with an IIR filter to achieve the narrow transition bandwidth with relatively few filter coefficients. Zero-stuffing and filtering are used to achieve the interpolation. A forward-backward filtering methodology is then used to achieve a linear phase response for the IIR filter. The input sequence to be interpolated is zero stuffed and passed through the IIR filter a first time. Then the time order of the resulting sequence is reversed and then passed through the IIR filter a second time. After that, the resulting output sequence is reversed again. Guard blocks are added to both ends of the input sequence, and then a block of zeros is appended to the zero-stuffed guarded input sequence. The appended zero block causes the startup and ending transient effect of the IIR filter's step response to be equal at both ends, which tends to improve the accuracy of the interpolation. Subsequent zero-stuffing and filtering by FIR filter stages are used to further increase the interpolation. A linear interpolator may also be included after the FIR filter stages.
摘要翻译： 具有线性相位响应的内插器具有用IIR滤波器实现的第一级，以通过相对较少的滤波器系数实现窄的转换带宽。 零填充和过滤用于实现插值。 然后使用前向后向滤波方法来实现IIR滤波器的线性相位响应。 待内插的输入序列为零填充并首次通过IIR滤波器。 然后将得到的序列的时间顺序颠倒，然后再次通过IIR滤波器。 之后，结果输出序列再次反转。 保护块被添加到输入序列的两端，然后将零块附加到零填充保护输入序列。 附加的零块导致IIR滤波器的阶跃响应的启动和结束瞬态效应在两端相等，这倾向于提高插值的精度。 随后使用FIR滤波器进行零填充和滤波，以进一步增加插值。 在FIR滤波器级之后也可以包括线性内插器。
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公开(公告)号：US6049577A
公开(公告)日：2000-04-11
申请号：US86794
申请日：1998-05-28
摘要： A pattern detector adapted for wireless communication systems includes an error calculator, a comb filter, an averager, and a threshold detector. The pattern to be detected is a sequence of pilot signal patterns whose error calculation is relatively invariant with respect to frequency offset introduced by Doppler and the local oscillator. The pattern detector processes received input samples y.sub.k to determine an error signal from the input samples y.sub.k and estimated input samples y.sub.k. The estimated input samples y.sub.k are determined using an estimated channel impulse response. When a vector of the received input samples is "aligned" with the expected header sync input samples, the level of the error signal is about equal to the level of the noise. The pattern detector determines the average level of the error signals for the last K error signals of each sample position E.sub.Kn within a pilot pattern, where K corresponds to the number of pilot patterns in a header sync pattern and n corresponds to the sample position. The pattern detector also determines the average level of the error signals E.sub.L corresponding to the last L received input samples, where L corresponds to the number of samples in a header sync sequence. When E.sub.Kn for a sample position is lower than a preselected threshold percentage of E.sub.L, the header sync pattern is deemed detected. Finally, the end of the header sync pattern is determined by the location of the minimum E.sub.Kn. This minimum is found by calculating, once the header is deemed detected, values for E.sub.Kn that are a certain number of samples past the last minimum.
摘要翻译： 适用于无线通信系统的模式检测器包括误差计算器，梳状滤波器，平均器和阈值检测器。 要检测的模式是导频信号模式的序列，其误差计算相对于由多普勒和本地振荡器引入的频率偏移是相对不变的。 模式检测器处理接收到的输入样本+ E，ovs y + EE k，以从输入样本+ E，ovs y + EE k和估计输入样本+ E，cir y + EE k确定误差信号。 使用估计的信道脉冲响应确定估计输入样本+ E，cir y + EE k。 当所接收的输入采样的矢量与期望的报头同步输入采样“对准”时，误差信号的电平约等于噪声的电平。 模式检测器确定导频模式中每个采样位置EKn的最后K个误差信号的误差信号的平均电平，其中K对应于报头同步模式中的导频模式的数量，n对应于采样位置。 模式检测器还确定对应于最后L个接收输入采样的误差信号EL的平均电平，其中L对应于报头同步序列中的采样数。 当采样位置的EKn低于EL的预选阈值百分比时，认为检测到标题同步模式。 最后，头部同步模式的结束由最小EKn的位置决定。 通过计算找到该最小值，一旦检测到标题，则EKn的值超过了最后一个最小值的一定数量的样本。
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公开(公告)号：US5732333A
公开(公告)日：1998-03-24
申请号：US601118
申请日：1996-02-14
申请人： Charles Brian Cox , David Kent Bonds , Jay Jui-Chieh Chen , Flaviu C. Costescu , Joel Richard Dierks , Wayne Douglas Duello , Thomas L. Frederick , Paul A. Goud , Derek Stephen Hilborn , Richard Johnathan Hinkle , Terry Lee Hinkle , David E. Jones , Theron Lee Jones , Patricia Fern Kavanagh , David W. Kroeger , Robert Richard Leyendecker , Vladimir Pavlovic , Claudio Gustavo Rey , Ray M.R. Sewlochan , Emre Tapucu , Mark A. Walker
发明人： Charles Brian Cox , David Kent Bonds , Jay Jui-Chieh Chen , Flaviu C. Costescu , Joel Richard Dierks , Wayne Douglas Duello , Thomas L. Frederick , Paul A. Goud , Derek Stephen Hilborn , Richard Johnathan Hinkle , Terry Lee Hinkle , David E. Jones , Theron Lee Jones , Patricia Fern Kavanagh , David W. Kroeger , Robert Richard Leyendecker , Vladimir Pavlovic , Claudio Gustavo Rey , Ray M.R. Sewlochan , Emre Tapucu , Mark A. Walker
CPC分类号： H03C3/406 , H03F1/3247 , H03F1/3294 , H03F2201/3233 , H04B2001/0425
摘要： A linear transmitter (101) using predistortion includes a modulator (103), a predistorter (107), a digital quadrature modulator (111), an upconverter (113), a power amplifier (115), and an antenna (117). In addition, the transmitter (101) has a feedback loop including a coupler (119), a downconverter (123), a digital quadrature demodulator (125), and a trainer (131). The digital data to be transmitted is provided into the modulator (103), which converts the digital data into in-phase and quadrature component signals. The in-phase and quadrature component signals are then provided to the predistorter (107), which "predistorts" the component signals prior to amplification. The digital quadrature modulator (111) converts the component signals into a single analog signal. The upconverter (113) upconverts this signal from the predistorter (107) into the desired frequency of transmission, which is provided to the power amplifier (115) and the antenna (117) for amplification and broadcast. The coupler (119) provides a portion of the amplified signal to the analog downconverter (123), which lowers the frequency of this signal to a range that is easily processed. The signal is then provided to the digital quadrature demodulator (125), which outputs the in-phase and quadrature component signals of the signal. These in-phase and quadrature component signals are provided to the trainer (131) which analyzes them with the output signals from the modulator. The trainer (131) compares these signals and updates the predistorter (107) so that the digital quadrature demodulator (125) output signals are substantially equivalent to the modulator (103) output signals.
摘要翻译： 使用预失真的线性发射机（101）包括调制器（103），预失真器（107），数字正交调制器（111），上变频器（113），功率放大器（115）和天线（117）。 另外，发射机（101）具有包括耦合器（119），下变频器（123），数字正交解调器（125）和训练器（131）的反馈回路。 要发送的数字数据被提供给调制器（103），其将数字数据转换成同相和正交分量信号。 然后将同相和正交分量信号提供给预失真器（107），其在放大之前“分段”分量信号。 数字正交调制器（111）将分量信号转换为单个模拟信号。 上变频器（113）将该信号从预失真器（107）上变频成期望的发送频率，其被提供给用于放大和广播的功率放大器（115）和天线（117）。 耦合器（119）将放大信号的一部分提供给模拟下变频器（123），这将该信号的频率降低到容易处理的范围。 然后将信号提供给数字正交解调器（125），其输出信号的同相和正交分量信号。 这些同相和正交分量信号被提供给训练器（131），其利用来自调制器的输出信号对它们进行分析。 训练器（131）比较这些信号并更新预失真器（107），使得数字正交解调器（125）输出信号基本上等于调制器（103）的输出信号。
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