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公开(公告)号：US11228287B2
公开(公告)日：2022-01-18
申请号：US16903771
申请日：2020-06-17
Applicant: Cree, Inc.
Inventor： Madhu Chidurala , Marvin Marbell , Niklas Thulin
Abstract: An electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network.
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公开(公告)号：US20200304074A1
公开(公告)日：2020-09-24
申请号：US16358985
申请日：2019-03-20
Applicant: Cree, Inc.
Inventor： Haedong Jang , Sonoko Aristud , Marvin Marbell , Madhu Chidurala
Abstract: In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier. In other embodiments shunt inductances and/or capacitors may be added to one or both amplifiers, and sized to effectively control a characteristic impedance of the impedance inverter.
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公开(公告)号：US20210399692A1
公开(公告)日：2021-12-23
申请号：US16903771
申请日：2020-06-17
Applicant: Cree, Inc.
Inventor： Madhu Chidurala , Marvin Marbell , Niklas Thulin
Abstract: An electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network.
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公开(公告)号：US20210313283A1
公开(公告)日：2021-10-07
申请号：US17031745
申请日：2020-09-24
Applicant: Cree, Inc.
Inventor： Richard Wilson , Madhu Chidurala
IPC: H01L23/66 , H01L25/18 , H01L23/498 , H01L23/00
Abstract: A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.
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公开(公告)号：US20210408978A1
公开(公告)日：2021-12-30
申请号：US16910900
申请日：2020-06-24
Applicant: Cree, Inc.
Inventor： Madhu Chidurala , Richard Wilson , Haedong Jang , Simon Ward
IPC: H03F3/195 , H03F1/56 , H01L23/047 , H01L23/367 , H01L23/66 , H01L23/00 , H01L25/16
Abstract: A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.
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Patent Agency Ranking
公开(公告)号：US20210280478A1
公开(公告)日：2021-09-09
申请号：US16811161
申请日：2020-03-06
Applicant: Cree, Inc.
Inventor： Richard Wilson , Haedong Jang , Simon Ward , Madhu Chidurala
IPC: H01L23/043 , H01L23/495 , H01L21/48
Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.
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公开(公告)号：US12224217B2
公开(公告)日：2025-02-11
申请号：US16811161
申请日：2020-03-06
Applicant: Cree, Inc.
Inventor： Richard Wilson , Haedong Jang , Simon Ward , Madhu Chidurala
IPC: H01L23/043 , H01L21/48 , H01L23/495
Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.
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公开(公告)号：US11201591B2
公开(公告)日：2021-12-14
申请号：US16358985
申请日：2019-03-20
Applicant: Cree, Inc.
Inventor： Haedong Jang , Sonoko Aristud , Marvin Marbell , Madhu Chidurala
Abstract: In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier. In other embodiments shunt inductances and/or capacitors may be added to one or both amplifiers, and sized to effectively control a characteristic impedance of the impedance inverter.
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公开(公告)号：US20210265249A1
公开(公告)日：2021-08-26
申请号：US16797290
申请日：2020-02-21
Applicant: Cree, Inc.
Inventor： Alexander Komposch , Simon Ward , Madhu Chidurala
IPC: H01L23/498 , H01L23/66
Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.
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公开(公告)号：US11257740B2
公开(公告)日：2022-02-22
申请号：US16797290
申请日：2020-02-21
Applicant: Cree, Inc.
Inventor： Alexander Komposch , Simon Ward , Madhu Chidurala
IPC: H01L23/498 , H01L23/66
Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.
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