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公开(公告)号：US20120131312A1
公开(公告)日：2012-05-24
申请号：US13137948
申请日：2011-09-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.
摘要翻译： 数据处理装置2包括处理电路4和指令解码器6.位
域操作指令控制处理装置2，从对应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。 比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值 具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。-
2.发明授权Apparatus and method for processing a bitfield manipulation instruction having a control value indicating insertion or extraction form 有权用于处理具有指示插入或提取形式的控制值的位域操作指令的装置和方法公开(公告)号：US09207937B2
公开(公告)日：2015-12-08
申请号：US13137948
申请日：2011-09-22
CPC分类号： G06F9/3016 , G06F7/764 , G06F7/768 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/30145 , G06F9/3887
摘要： A data processing apparatus comprises a processing circuit and instruction decoder. A bitfield manipulation instruction controls the processing apparatus to generate at least one result data element from corresponding first and second source data elements. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element. Bits of the result data element that are more significant than the inserted bitfield have a prefix value that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element, and a third prefix value corresponding to a sign extension of the bitfield of the first source data element.
摘要翻译： 数据处理装置包括处理电路和指令译码器。 位
域操作指令控制处理装置，从对应的第一和第二源数据元素生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素的位字段bf的部分。 结果数据元素比插入的位域更重要的位具有基于由指令指定的控制值而被选择的前缀值作为具有零值的第一前缀值之一，具有第二前缀值的前缀值具有 相应的第二源数据元素的一部分的值，以及与第一源数据元素的位域的符号扩展对应的第三前缀值。-
公开(公告)号：US20120089817A1
公开(公告)日：2012-04-12
申请号：US13200348
申请日：2011-09-23
IPC分类号： G06F9/30
CPC分类号： G06F9/30003 , G06F9/30072 , G06F9/30094 , G06F9/3842
摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register; a data processor configured to perform data processing operations controlled by the instruction decoder wherein: the data processor is responsive to the decoded at least one conditional select instruction and the condition having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register; and the data processor is responsive to the decoded at least one conditional select instruction and the condition not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
摘要翻译： 一种数据处理装置，方法和计算机程序，其对诸如寄存器的一个数据元素执行操作，然后有条件地选择该寄存器或其上没有进行任何操作的另外的寄存器。 该装置包括：指令解码器，被配置为对至少一个条件选择指令进行解码，所述至少一个条件选择指令指定主源寄存器，次源寄存器，目的地寄存器，条件以及对数据执行的操作 来自次级源寄存器的元件; 配置为执行由指令解码器控制的数据处理操作的数据处理器，其中：数据处理器响应于解码的至少一个条件选择指令和具有预定结果的条件，以从次级源寄存器对数据元素执行操作 以形成结果数据元素并将结果数据元素存储在目的寄存器中; 并且数据处理器响应于解码的至少一个条件选择指令和不具有预定结果的条件，以从主寄存器的数据元素形成结果数据元素，并将结果数据元素存储在目的寄存器中。
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公开(公告)号：US09753724B2
公开(公告)日：2017-09-05
申请号：US13200348
申请日：2011-09-23
CPC分类号： G06F9/30003 , G06F9/30072 , G06F9/30094 , G06F9/3842
摘要： A data processing apparatus, method and computer program that perform an operation on one data element such as a register and conditionally select either that register or a further register on which no operation has been performed. The apparatus includes an instruction decoder configured to decode at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. Data processing operations are controlled by the instruction decoder and the data processor is responsive to the decoded at least one conditional select instruction where the condition does not have the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.
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公开(公告)号：US08954711B2
公开(公告)日：2015-02-10
申请号：US13361229
申请日：2012-01-30
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译： 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。
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6.发明授权Mixed operand size instruction processing for execution of indirect addressing load instruction specifying registers for different size operands 有权用于执行间接寻址加载指令的混合操作数大小指令处理指定用于不同大小操作数的寄存器公开(公告)号：US09009450B2
公开(公告)日：2015-04-14
申请号：US13353805
申请日：2012-01-19
CPC分类号： G06F9/30149 , G06F9/30043 , G06F9/30098 , G06F9/3016 , G06F9/30192 , G06F9/345 , G06F9/355
摘要： A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.
摘要翻译： 数据处理系统2包括处理器核心4和存储器6.处理器核心4包括由解码器电路24产生的控制信号控制的处理电路12,14,16,18,26，其解码程序指令。 程序指令包括具有第一操作数大小的第一输入操作数和第二输入操作数大小的第二输入操作数的混合操作数大小指令（加载/存储指令或算术指令），其中第二操作数大小小于第一操作数大小 操作数大小。 所执行的处理首先将第二操作数转换为具有第一操作数大小。 然后，处理使用第一操作数大小的第一操作数作为输入并且现在转换为具有第一操作数大小的第二操作数作为输入产生第三操作数。
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公开(公告)号：US20120233444A1
公开(公告)日：2012-09-13
申请号：US13353805
申请日：2012-01-19
CPC分类号： G06F9/30149 , G06F9/30043 , G06F9/30098 , G06F9/3016 , G06F9/30192 , G06F9/345 , G06F9/355
摘要： A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.
摘要翻译： 数据处理系统2包括处理器核心4和存储器6.处理器核心4包括由解码器电路24产生的控制信号控制的处理电路12,14,16,18,26，其解码程序指令。 程序指令包括具有第一操作数大小的第一输入操作数和第二输入操作数大小的第二输入操作数的混合操作数大小指令（加载/存储指令或算术指令），其中第二操作数大小小于第一操作数大小 操作数大小。 所执行的处理首先将第二操作数转换为具有第一操作数大小。 然后，处理使用第一操作数大小的第一操作数作为输入并且现在转换为具有第一操作数大小的第二操作数作为输入产生第三操作数。
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公开(公告)号：US20120233440A1
公开(公告)日：2012-09-13
申请号：US13361229
申请日：2012-01-30
IPC分类号： G06F12/00
CPC分类号： G06F9/3557 , G06F9/30007 , G06F9/30112 , G06F9/30167 , G06F9/342 , G06F9/345 , G06F2212/657
摘要： A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.
摘要翻译： 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。
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9.发明申请Low-overhead/power-saving processor synchronization mechanism, and applications thereof 审中-公开低架空/省电处理器同步机制及其应用公开(公告)号：US20090063881A1
公开(公告)日：2009-03-05
申请号：US11896424
申请日：2007-08-31
申请人： Nigel John Stephens
发明人： Nigel John Stephens
CPC分类号： G06F1/3203 , G06F1/329 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/30123 , G06F9/3851 , G06F9/3885 , Y02D10/24 , Y02D50/20
摘要： A low-overhead/power-saving processor synchronization mechanism, and applications thereof. In an embodiment, the present invention provides a processor having a load-linked register. The processor implements instructions related to the load-linked register. A first instruction, when executed by the processor, causes the processor to load a first value specified by the first instruction in a first register of a register file and to load a second value in the load-linked register. A second instruction, when executed by the processor, causes the processor to suspend execution of a stream of instructions associated with the load-linked register if the second value in the load-linked register is unaltered until the second value in the load-linked register is altered. A third instruction, when executed by the processor, causes the processor to conditionally move a third value to a memory location specified by the third instruction and to move a value representing the state of the load-linked register to the third register.
摘要翻译： 低架空/省电处理器同步机制及其应用。 在一个实施例中，本发明提供一种具有负载连接寄存器的处理器。 处理器实现与负载链接寄存器相关的指令。 当由处理器执行时，第一指令使处理器将由第一指令指定的第一值加载到寄存器堆的第一寄存器中，并在加载链接寄存器中加载第二值。 第二条指令在由处理器执行时，如果加载链接寄存器中的第二个值不变，直到加载链接寄存器中的第二个值，处理器将暂停执行与加载链接寄存器相关联的指令流 被改变 第三指令在由处理器执行时使处理器有条件地将第三值移动到由第三指令指定的存储器位置，并将表示加载链接寄存器的状态的值移动到第三寄存器。
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