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1.发明申请Method and apparatus for implementing power saving for content addressable memory 审中-公开实现内容可寻址存储器省电的方法和装置公开(公告)号：US20070047282A1
公开(公告)日：2007-03-01
申请号：US11216385
申请日：2005-08-31
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/22 , G11C7/225 , G11C2207/2227
摘要： A method and apparatus are provided for implementing power saving in a content addressable memory (CAM). A compare array is matched against a key and if a match occurs then logic coupled to the compare array generates a hit signal. A data array includes precharge circuitry and data output latches to capture the data output. A clock gate coupled to the logic provides clock signals to the output latches and precharge circuitry of the data array when a hit occurs. When a hit does not occur, the clock signals are gated off to the output latches and precharge circuitry of the data array.
摘要翻译： 提供了一种用于在内容可寻址存储器（CAM）中实现功率节省的方法和装置。 比较数组与键匹配，如果发生匹配，则与比较数组相耦合的逻辑产生命中信号。 数据阵列包括预充电电路和数据输出锁存器来捕获数据输出。 耦合到逻辑的时钟门在发生命中时向数据阵列的输出锁存器和预充电电路提供时钟信号。 当不发生命中时，时钟信号被门控到数据阵列的输出锁存器和预充电电路。
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公开(公告)号：US20050034037A1
公开(公告)日：2005-02-10
申请号：US10636060
申请日：2003-08-07
申请人： Derick Behrends , Peter Freiburger , Ryan Kivimagi
发明人： Derick Behrends , Peter Freiburger , Ryan Kivimagi
CPC分类号： G11C29/12
摘要： In a first aspect, a first method is provided for testing an integrated circuit (IC). The first method includes the steps of (1) selecting a bit from each of a plurality of memory arrays formed on an IC chip; (2) selecting one of the plurality of memory arrays; and (3) storing the selected bit from the selected memory array. Numerous other aspects are provided.
摘要翻译： 在第一方面，提供了一种用于测试集成电路（IC）的方法。 第一种方法包括以下步骤：（1）从形成在IC芯片上的多个存储器阵列中的每一个选择位; （2）选择多个存储器阵列中的一个; 和（3）从选择的存储器阵列存储所选位。 提供了许多其他方面。
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3.发明申请公开(公告)号：US20070053231A1
公开(公告)日：2007-03-08
申请号：US11552791
申请日：2006-10-25
申请人： Chad Adams , Derick Behrends , Ryan Kivimagi
发明人： Chad Adams , Derick Behrends , Ryan Kivimagi
IPC分类号： G11C7/00
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
摘要翻译： 提供了一种方法，装置和计算机程序产品，用于采用连续位线局部评估电路的SRAM单元的泛洪模式实现。 洪水模式测试用于通过强调SRAM单元来清除边缘SRAM单元。 通过开始正常的写操作来引发洪泛模式。 在新的数据值被强制进入SRAM单元之后，写入信号被切断。 延迟块将字线信号保持在高电源，SRAM单元进入泛洪模式。 在这个关键点，边缘细胞可以很容易地被检测，并且稍后映射到冗余细胞。
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公开(公告)号：US20070018690A1
公开(公告)日：2007-01-25
申请号：US11186608
申请日：2005-07-21
申请人： Derick Behrends , Ryan Kivimagi , Chihhung Liao
发明人： Derick Behrends , Ryan Kivimagi , Chihhung Liao
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An apparatus and method provide logically controlled masking of one or more maskable data bits from a plurality of data bits that are input to a dynamic logic circuit. No masking logic and attendant delay penalty is coupled in the data path that is not needed for unmasked bits from the plurality of data bits that do not need masking. A system clock has a precharge phase and an evaluate phase. A first clock buffer is coupled to a precharge switch and precharges a dynamic node during the precharge phase. A second clock buffer having substantially the same delay from system clock input to an output of the second clock buffer is gated by a derivative of a mask. The output of the second clock buffer controls one or more switches in series with switches controlled by the maskable data bits.
摘要翻译： 一种装置和方法从输入到动态逻辑电路的多个数据位提供一个或多个可屏蔽数据位的逻辑控制掩蔽。 在不需要掩蔽的多个数据位中的未屏蔽位不需要的数据路径中耦合掩蔽逻辑和伴随的延迟损耗。 系统时钟具有预充电阶段和评估阶段。 第一时钟缓冲器耦合到预充电开关并且在预充电阶段期间预充电动态节点。 具有从系统时钟输入到第二时钟缓冲器的输出的基本相同延迟的第二时钟缓冲器由掩模的导数来选通。 第二时钟缓冲器的输出控制与由可屏蔽数据位控制的开关串联的一个或多个开关。
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5.发明申请Glitch protect valid cell and method for maintaining a desired state value 有权毛刺保护有效的单元格和方法以保持所需的状态值公开(公告)号：US20070019454A1
公开(公告)日：2007-01-25
申请号：US11184346
申请日：2005-07-19
IPC分类号： G11C15/00
摘要： A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate. In a glitch protect condition, the glitch protect valid cell restores the initial logic state value of the true valid bit despite at least one glitch signal invalidating the initial value. As such, the first pull down network resets the initial state value of the true valid bit according to the timing signal and the glitch signal supplied to the glitch protect circuit. The initial state value of a true valid bit is restored in the memory element with the second pull down network via the timing signal and a restore signal provided by an enabled pull up network within the NOR gate. Specifically, the second pull down network is responsive to the pull up network selectively enabled within the NOR gate and resets the complement valid bit in the memory element to consequently restore the initial state value of the true valid bit.
摘要翻译： 毛刺保护有效单元和方法，用于响应于毛刺信号和定时信号来维持所需的逻辑状态值。 毛刺保护有效单元可以与内容可寻址存储器（CAM）阵列集成，用于指示存储在CAM内的字数据是否有效。 毛刺保护有效单元包括每个彼此响应的存储元件，状态机和毛刺保护电路。 毛刺保护电路包括彼此电耦合的传播延迟组件和恢复组件。 传播延迟组件包括彼此电耦合的第一下拉网络和或非门极。 恢复组件包括电耦合到传播延迟组件的第二下拉网络。 第一下拉网络响应于毛刺信号和定时信号以选择性地接合或非门。 在毛刺保护条件下，尽管至少有一个毛刺信号使初始值无效，但毛刺保护有效单元仍恢复真有效位的初始逻辑状态值。 这样，第一下拉网络根据提供给毛刺保护电路的定时信号和毛刺信号来重置真有效位的初始状态值。 通过定时信号，通过第二下拉网络在存储器元件中恢复真有效位的初始状态值，以及由或非门内由使能的上拉网络提供的恢复信号。 具体地，第二下拉网络响应于在或非门内选择性启用的上拉网络，并且重置存储器元件中的补码有效位，从而恢复真有效位的初始状态值。
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公开(公告)号：US20060092727A1
公开(公告)日：2006-05-04
申请号：US10981153
申请日：2004-11-04
申请人： Chad Adams , Derick Behrends , Ryan Kivimagi
发明人： Chad Adams , Derick Behrends , Ryan Kivimagi
摘要： A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood mode is induced by beginning with a normal write operation. After new data values have been forced into the SRAM cells, then the write signal is chopped off. A delay block keeps the wordline signal at the high supply, and the SRAM cells go into flood mode. At this juncture marginal cells can be easily detected and later mapped to redundant cells.
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