公开(公告)号：US20070019454A1

公开(公告)日：2007-01-25

申请号：US11184346

申请日：2005-07-19

申请人： Derick Behrends ,  Chad Adams ,  Ryan Kivimagi ,  Anthony Aipperspach ,  Robert Krentler

发明人： Derick Behrends ,  Chad Adams ,  Ryan Kivimagi ,  Anthony Aipperspach ,  Robert Krentler

IPC分类号： G11C15/00

CPC分类号： G11C15/00 ,  G11C7/24

摘要： A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate. In a glitch protect condition, the glitch protect valid cell restores the initial logic state value of the true valid bit despite at least one glitch signal invalidating the initial value. As such, the first pull down network resets the initial state value of the true valid bit according to the timing signal and the glitch signal supplied to the glitch protect circuit. The initial state value of a true valid bit is restored in the memory element with the second pull down network via the timing signal and a restore signal provided by an enabled pull up network within the NOR gate. Specifically, the second pull down network is responsive to the pull up network selectively enabled within the NOR gate and resets the complement valid bit in the memory element to consequently restore the initial state value of the true valid bit.

摘要翻译： 毛刺保护有效单元和方法，用于响应于毛刺信号和定时信号来维持所需的逻辑状态值。 毛刺保护有效单元可以与内容可寻址存储器（CAM）阵列集成，用于指示存储在CAM内的字数据是否有效。 毛刺保护有效单元包括每个彼此响应的存储元件，状态机和毛刺保护电路。 毛刺保护电路包括彼此电耦合的传播延迟组件和恢复组件。 传播延迟组件包括彼此电耦合的第一下拉网络和或非门极。 恢复组件包括电耦合到传播延迟组件的第二下拉网络。 第一下拉网络响应于毛刺信号和定时信号以选择性地接合或非门。 在毛刺保护条件下，尽管至少有一个毛刺信号使初始值无效，但毛刺保护有效单元仍恢复真有效位的初始逻辑状态值。 这样，第一下拉网络根据提供给毛刺保护电路的定时信号和毛刺信号来重置真有效位的初始状态值。 通过定时信号，通过第二下拉网络在存储器元件中恢复真有效位的初始状态值，以及由或非门内由使能的上拉网络提供的恢复信号。 具体地，第二下拉网络响应于在或非门内选择性启用的上拉网络，并且重置存储器元件中的补码有效位，从而恢复真有效位的初始状态值。

公开(公告)号：US20050007813A1

公开(公告)日：2005-01-13

申请号：US10616847

申请日：2003-07-10

申请人： Chad Adams ,  Anthony Aipperspach ,  Todd Christensen ,  Peter Freiburger

发明人： Chad Adams ,  Anthony Aipperspach ,  Todd Christensen ,  Peter Freiburger

IPC分类号： G11C7/18 ,  G11C11/419 ,  G11C11/00

CPC分类号： G11C7/18 ,  G11C11/419

摘要： The present invention provides for reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.

摘要翻译： 本发明提供从SRAM单元读取标记。 在写真线上生成一个低值。 在连续的位线上生成高值。 通过使用耦合到SRAM单元的真实节点的浮动电压来评估SRAM单元的真实节点。 如果浮置电压保持大致恒定，则从SRAM单元读取的值为高。 如果浮置电压耗尽地，则从SRAM单元读取的值为低电平。

公开(公告)号：US20070019461A1

公开(公告)日：2007-01-25

申请号：US11186606

申请日：2005-07-21

申请人： Chad Adams ,  Anthony Aipperspach ,  Juergen Pille ,  Otto Wagner

发明人： Chad Adams ,  Anthony Aipperspach ,  Juergen Pille ,  Otto Wagner

IPC分类号： G11C11/00

CPC分类号： G11C11/413 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/12

摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了访问存储器的第一种方法。 第一种方法包括以下步骤：（1）将包含在具有排列成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括一组晶体管，其适合于存储该位并影响被断言的信号 在耦合到所述单元的位线上的读取操作期间，所述受影响的信号与存储在所述单元中的所述位的值相匹配; 并且（2）防止存储在单元中的位的值改变状态，同时晶体管组影响在耦合到单元的位线的读操作期间断言的信号。 提供了许多其他方面。

公开(公告)号：US20070044049A1

公开(公告)日：2007-02-22

申请号：US11207068

申请日：2005-08-18

申请人： Chad Adams ,  Anthony Aipperspach ,  George Paulik

发明人： Chad Adams ,  Anthony Aipperspach ,  George Paulik

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.

摘要翻译： 用于由于过程缺陷和/或设备变化而预测和/或校准存储器的装置和方法，包括确定存储器单元的模型，识别与模型相关联的参数的子集，使用 参数，基于精炼模型的模拟操作确定模拟存储器单元将可操作的预测概率，根据预测概率确定收益率预测信息，以及确定修复元素的最小数量以包括在存储器阵列设计中以确保 基于产量预测信息的期望产量百分比。

公开(公告)号：US20060250842A1

公开(公告)日：2006-11-09

申请号：US11122805

申请日：2005-05-05

申请人： Chad Adams ,  Anthony Aipperspach

发明人： Chad Adams ,  Anthony Aipperspach

IPC分类号： G11C14/00

CPC分类号： G11C11/412

摘要： In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a first group of transistors adapted to store the bit and a second group of transistors adapted to affect a signal asserted during a read operation on a read bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the second group of transistors affects the signal asserted during the read operation on the read bit line coupled to the cell. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了访问存储器的第一种方法。 第一种方法包括以下步骤：（1）将包含在具有布置成行和列的多个单元的存储器中的单元中存储位，其中每个单元包括适于存储该位的第一组晶体管和第二组 晶体管适于影响在耦合到该单元的读取位线上的读取操作期间所确定的信号，使得受影响的信号与存储在该单元中的位的值相匹配; 和（2）防止存储在单元中的位的值改变状态，而第二组晶体管影响在读取操作期间对耦合到该单元的读位线断言的信号。 提供了许多其他方面。

公开(公告)号：US20050134360A1

公开(公告)日：2005-06-23

申请号：US10744175

申请日：2003-12-23

申请人： Anthony Aipperspach ,  William Hovis ,  Terrance Kueper ,  John Sheets

发明人： Anthony Aipperspach ,  William Hovis ,  Terrance Kueper ,  John Sheets

IPC分类号： G11C7/04 ,  G11C7/10

CPC分类号： G11C7/04 ,  G11C7/1045

摘要： Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress condition. Many storage elements in an electronic system store the same data for virtually the life of the system, resulting in significant BTI caused VT shifts in FETs in the storage elements. An embodiment of the invention ensures that a particular storage element is in a first state for a first portion of time the electronic system operates, during which data is stored in a storage element in a first phase, and that the particular storage element is in a second state for a second portion of time the electronic system operates, during which data is stored in the storage element in a second phase.

摘要翻译： 公开了允许用场效应晶体管（FET）实现的电子系统减少由偏置温度不稳定性（BTI）引起的阈值电压偏移的方法和装置。 当FET处于特定的电压应力状态时，BTI引起VT偏移累加。 电子系统中的许多存储元件几乎在系统中存储相同的数据，导致显着的BTI导致存储元件中FET的VT位移。 本发明的一个实施例确保了特定存储元件在电子系统操作的第一时间段处于第一状态，在此期间数据被存储在第一阶段的存储元件中，并且特定存储元件处于 电子系统操作的第二部分时间的第二状态，在此期间数据以第二阶段存储在存储元件中。

公开(公告)号：US20060156091A1

公开(公告)日：2006-07-13

申请号：US11023677

申请日：2004-12-28

申请人： Anthony Aipperspach ,  Louis Bushard ,  Akihiko Fukui ,  Garrett Koch

发明人： Anthony Aipperspach ,  Louis Bushard ,  Akihiko Fukui ,  Garrett Koch

IPC分类号： G11C29/00

CPC分类号： G11C29/32 ,  G11C29/16 ,  G11C2029/3202

摘要： In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.

公开(公告)号：US20050010885A1

公开(公告)日：2005-01-13

申请号：US10616881

申请日：2003-07-10

申请人： Anthony Aipperspach ,  David Boerstler ,  Dieter Wendel

发明人： Anthony Aipperspach ,  David Boerstler ,  Dieter Wendel

IPC分类号： G06F9/45 ,  G06F17/50 ,  H03K5/156 ,  H03L7/06

CPC分类号： H03K5/1565 ,  H03L7/06

摘要： A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.

摘要翻译： 提供了一种用于限制电路的芯片时钟设计中的脉冲宽度的方法和装置。 该电路接收具有时钟脉冲宽度的时钟信号。 检测时钟信号的时钟脉冲宽度。 确定时钟脉冲宽度是否大于最大时钟脉冲宽度。 在确定时钟脉冲宽度大于最大时钟脉冲宽度的情况下，时钟信号的时钟脉冲宽度受到限制。

公开(公告)号：US20060044020A1

公开(公告)日：2006-03-02

申请号：US10926897

申请日：2004-08-26

申请人： Anthony Aipperspach ,  Peter Freiburger

发明人： Anthony Aipperspach ,  Peter Freiburger

IPC分类号： H03K19/20

CPC分类号： H03K19/0963

摘要： A latching dynamic logic includes a dynamic logic gate, a static logic input interface, and a set-reset output latch. The dynamic logic gate receives a clock signal, a data signal, and a select signal output of the static logic input interface. The dynamic logic gate includes a dynamic node and a pulldown network coupled to the dynamic node. The pulldown network selectively discharges the dynamic node following a clock signal transition dependent on the data signal and the select signal output of the static logic input interface being active. The set-reset output latch is coupled to the dynamic node of the dynamic logic gate for providing an output signal.

摘要翻译： 锁存动态逻辑包括动态逻辑门，静态逻辑输入接口和置位复位输出锁存器。 动态逻辑门接收静态逻辑输入接口的时钟信号，数据信号和选择信号输出。 动态逻辑门包括耦合到动态节点的动态节点和下拉网络。 下拉网络根据数据信号的时钟信号转换和静态逻辑输入接口的选择信号输出有效地选择性地放电动态节点。 设置复位输出锁存器耦合到动态逻辑门的动态节点，用于提供输出信号。

公开(公告)号：US20050091620A1

公开(公告)日：2005-04-28

申请号：US10692416

申请日：2003-10-23

申请人： Anthony Aipperspach ,  David Boerstler ,  Eskinder Hailu

发明人： Anthony Aipperspach ,  David Boerstler ,  Eskinder Hailu

IPC分类号： G06F1/04 ,  G06F9/45 ,  H03K5/04 ,  H03K5/156

CPC分类号： G06F1/04 ,  H03K5/04 ,  H03K5/1565

摘要： The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.

摘要翻译： 本发明提供使用增量延迟来校正过多的脉冲宽度。 通过校正块和泄漏检测器来评估脉冲宽度。 可接受的脉冲通过互连直接连接到时钟输出。 不可接受的脉冲通过块延迟模块发送，该模块延迟模块包含一系列根据预编程的总延迟时间断开和复位的延迟子块。 经调节的时钟脉冲通过节点重新发送到校正块和泄漏检测器，在那里它被重新评估。 如果脉冲是可接受的，则将其发送到时钟输出。 如果发现脉冲不可接受，则再次被再循环。 高时钟脉冲穿梭确定并改变时钟脉冲的高或低状态，以确保向下游相关设备输出正确的输出。