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    Method of controlled low-k via etch for Cu interconnections
    3.
    发明授权
    Method of controlled low-k via etch for Cu interconnections 有权
    用于Cu互连的受控低k通孔蚀刻的方法

    公开(公告)号：US07906426B2

    公开(公告)日：2011-03-15

    申请号：US11788969

    申请日：2007-04-23

    申请人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    发明人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

    摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

    摘要翻译： 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

    Method of controlled low-k via etch for Cu interconnections
    4.
    发明申请
    Method of controlled low-k via etch for Cu interconnections 有权
    用于Cu互连的受控低k通孔蚀刻的方法

    公开(公告)号：US20080258308A1

    公开(公告)日：2008-10-23

    申请号：US11788969

    申请日：2007-04-23

    申请人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    发明人： Wuping Liu ,  Johnny Widodo ,  Teck Jung Tang ,  Jing Hui Li ,  Han Wah Ng ,  Larry A. Clevenger ,  Hermann Wendt

    IPC分类号： H01L21/4763 ,  H01L21/76 ,  H01L29/40

    CPC分类号： H01L21/76802 ,  H01L21/02063 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31138

    摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.

    摘要翻译： 互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。 互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层 蚀刻停止层。 通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。 灰化将ILD的这部分转化为氧化物材料。 该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

    Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls
    5.
    发明申请
    Method of Forming Electrical Interconnects within Insulating Layers that Form Consecutive Sidewalls 有权
    在形成连续侧壁的绝缘层内形成电气互连的方法

    公开(公告)号：US20090239369A1

    公开(公告)日：2009-09-24

    申请号：US12051223

    申请日：2008-03-19

    申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    IPC分类号： H01L21/31 ,  H01L21/44

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

    摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

    摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。

    Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall
    6.
    发明授权
    Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall 有权
    在形成连续侧壁的绝缘层内形成电互连的方法，包括在内侧壁上形成反应层

    公开(公告)号：US07687381B2

    公开(公告)日：2010-03-30

    申请号：US12051223

    申请日：2008-03-19

    申请人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    发明人： Jae-hak Kim ,  Jing Hui Li ,  Wu Ping Liu ,  Johnny Widodo

    IPC分类号： H01L21/46 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76814 ,  H01L2221/1063

    摘要： Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.

    摘要翻译： 形成具有电互连的集成电路器件的方法包括在衬底上形成电绝缘层并在电绝缘层上形成硬掩模。 使用掩模依次选择性地蚀刻硬掩模和电绝缘层，以在其中限定开口。 该开口（其可以是通孔）暴露硬掩模和电绝缘层的内侧壁。 然后硬掩模的内侧壁相对于电绝缘层的内侧壁凹陷，并且牺牲反应层形成在电绝缘层的内侧壁上。 该反应层操作以使电绝缘层的内侧壁凹陷。 然后去除反应层以限定具有相对均匀侧壁的较宽开口。 然后用更宽的开口填充电互连。

    Interconnects with improved TDDB
    7.
    发明授权
    Interconnects with improved TDDB 有权
    与改进的TDDB互连

    公开(公告)号：US09281278B2

    公开(公告)日：2016-03-08

    申请号：US13286224

    申请日：2011-11-01

    申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

    发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

    摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。

    Interconnects with improved TDDB
    8.
    发明授权
    Interconnects with improved TDDB 有权
    与改进的TDDB互连

    公开(公告)号：US08053361B2

    公开(公告)日：2011-11-08

    申请号：US12203924

    申请日：2008-09-04

    申请人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

    发明人： Jing Hui Li ,  Wu Ping Liu ,  Lawrence A. Clevenger

    IPC分类号： H01L23/52

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A first upper etch stop layer is formed on the dielectric layer. The first upper etch stop layer includes a first dielectric material. The dielectric layer and first upper etch stop layer are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The interconnect and first upper etch stop layer have coplanar top surfaces. A second upper etch stop layer is formed over the coplanar top surfaces. The second upper etch stop layer includes a second material having sufficient adhesion with the first material to reduce diffusion of the conductive material.

    摘要翻译： 提出了一种形成半导体器件的方法。 提供了在其上形成有介电层的基板。 在介电层上形成第一上蚀刻停止层。 第一上蚀刻停止层包括第一电介质材料。 将电介质层和第一上蚀刻停止层图案化以形成互连开口。 互连开口填充有导电材料以形成互连。 互连和第一上蚀刻停止层具有共面的顶表面。 第二上蚀刻停止层形成在共面顶表面上。 第二上蚀刻停止层包括与第一材料具有足够粘合力以减少导电材料扩散的第二材料。