公开(公告)号：US20240213372A1

公开(公告)日：2024-06-27

申请号：US18487625

申请日：2023-10-16

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong Hae KIM ,  Jong-Heon YANG ,  Seong-Mok CHO ,  Ji Hun CHOI ,  Jae-Eun PI ,  Chi-Sun HWANG

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/41733 ,  H01L29/6675 ,  H01L29/66772 ,  H01L29/66969 ,  H01L29/78654 ,  H01L29/78672 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a method for manufacturing a vertical channel thin film transistor. The method for manufacturing the vertical channel thin film transistor includes forming a bottom source drain electrode, forming a first interlayer insulating layer, forming first middle source drain electrodes, forming a second interlayer insulating layer, forming a top source drain electrode, forming an opening through which portions of the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode are exposed, forming channel layers, forming a gate insulating layer on the channel layers, the bottom source drain electrode, the first middle source drain electrodes, and the top source drain electrode, and forming gate electrodes on the gate insulating layer.

公开(公告)号：US20240128653A1

公开(公告)日：2024-04-18

申请号：US18343068

申请日：2023-06-28

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong Hae KIM ,  Chi-Sun HWANG ,  Joo Yeon KIM ,  Jaehyun MOON ,  Jong-Heon YANG ,  Kyunghee CHOI ,  Ji Hun CHOI

IPC: H01Q15/00 ,  H01Q1/36 ,  H01Q15/14

CPC classification number: H01Q15/0086 ,  H01Q1/364 ,  H01Q15/148

Abstract: Disclosed is a meta-structure. The meta-structure includes a lower electrode, a lower insulating layer on the lower electrode, a lower metal oxide layer on the lower insulating layer, a metal layer on the lower metal oxide layer, an upper metal oxide layer on the metal layer, an upper insulating layer on the upper metal oxide layer, and antenna electrodes on the upper insulating layer.

公开(公告)号：US20240079413A1

公开(公告)日：2024-03-07

申请号：US18459147

申请日：2023-08-31

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Himchan OH ,  Jong-Heon YANG ,  Ji Hun CHOI ,  Seung Youl KANG ,  Yong Hae KIM ,  Jeho NA ,  Jaehyun MOON ,  Chan Woo PARK ,  Sung Haeng CHO ,  Jae-Eun PI ,  Chi-Sun HWANG

IPC: H01L27/12 ,  H10K59/121

CPC classification number: H01L27/1225 ,  H01L27/127 ,  H10K59/1213

Abstract: A complementary thin film transistor (TFT) includes a substrate and a first TFT and a second TFT disposed on the substrate, wherein a first conductive semiconductor layer of the first TFT and a second gate electrode layer of the second TFT are disposed in the same layer and include the same material.

公开(公告)号：US20220179359A1

公开(公告)日：2022-06-09

申请号：US17523197

申请日：2021-11-10

Applicant: Electronics and Telecommunications Research Institute ,  MVTECH

Inventor： Jae-Eun PI ,  Yong Hae KIM ,  Jong-Heon YANG ,  Chul Woong JOO ,  Chi-Sun HWANG ,  HA KYUN LEE ,  Seung Youl KANG ,  Gi Heon KIM ,  Joo Yeon KIM ,  Hee-ok KIM ,  Jeho NA ,  Jaehyun MOON ,  Won Jae LEE ,  Seong-Mok CHO ,  Ji Hun CHOI

IPC: G03H1/22 ,  G01B11/02 ,  G06T7/536

Abstract: Disclosed is an apparatus of analyzing a depth of a holographic image according to the present disclosure, which includes an acquisition unit that acquires a hologram, a restoration unit that restores a three-dimensional holographic image by irradiating the hologram with a light source, an image sensing unit that senses a depth information image of the restored holographic image, and an analysis display unit that analyzes a depth quality of the holographic image, based on the sensed depth information image, and the image sensing unit uses a lensless type of photosensor.

公开(公告)号：US20210124305A1

公开(公告)日：2021-04-29

申请号：US16988072

申请日：2020-08-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong Hae KIM ,  Seong-Mok CHO ,  Chi-Sun HWANG ,  Ji Hun CHOI ,  Gi Heon KIM ,  Jong-Heon YANG ,  Sang Hoon CHEON ,  Kyunghee CHOI ,  Jae-Eun PI

IPC: G03H1/22

Abstract: Provided are a hologram display device and a method of manufacturing the hologram display device. The hologram display device includes a light source unit that emits light, a spatial light modulator that modulates the light emitted from the light source unit, and a random pinhole panel. The random pinhole panel includes a plurality of pinholes of a random position or a random size and is arranged in line with an output part of the spatial light modulator. In the hologram display device and the method of manufacturing the hologram display device, a position and size of a random pinhole on the random pinhole are not limited to inside each pixel of the spatial light modulator.

公开(公告)号：US20190011791A1

公开(公告)日：2019-01-10

申请号：US16026970

申请日：2018-07-03

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ji Hun CHOI

IPC: G02F1/1362 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1335

Abstract: Provided is a display device. The display device includes a data line extending in a first direction, a reflective electrode on the data line, and a transistor formed between the data line and the reflective electrode. The transistor includes a first electrode connected to the data line, a second electrode spaced apart from the first electrode in the first direction and connected to the reflective electrode, and a semiconductor layer connecting the first electrode and the second electrode.

公开(公告)号：US20240061306A1

公开(公告)日：2024-02-22

申请号：US18342630

申请日：2023-06-27

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong Hae KIM ,  Chi-Sun HWANG ,  Kyunghee CHOI ,  Joo Yeon KIM ,  Jaehyun MOON ,  Jong-Heon YANG ,  Ji Hun CHOI

IPC: G02F1/19

CPC classification number: G02F1/19

Abstract: Disclosed is a meta-structure. The meta-structure includes a lower electrode, a lower insulating layer on the lower electrode, a lower metal oxide layer on the lower insulating layer, a lower metal layer on the lower metal oxide layer, a middle metal oxide layer on the lower metal layer, an upper metal layer on the middle metal oxide layer, an upper metal oxide layer on the upper metal layer, an upper insulating layer on the upper metal oxide layer, and antenna electrodes on the upper insulating layer.

公开(公告)号：US20220199836A1

公开(公告)日：2022-06-23

申请号：US17523320

申请日：2021-11-10

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE ,  Korea Advanced Institute of Science and Technology

Inventor： Chi-Sun HWANG ,  SangHee PARK ,  KwangHeum LEE ,  Jae-Eun PI ,  SeungHee LEE ,  Jong-Heon YANG ,  Ji Hun CHOI

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49

Abstract: A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.

公开(公告)号：US20230083225A1

公开(公告)日：2023-03-16

申请号：US17943528

申请日：2022-09-13

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jong-Heon YANG ,  Seung Youl KANG ,  Yong Hae KIM ,  Hee-ok KIM ,  Jeho NA ,  Jaehyun MOON ,  Chan Woo PARK ,  Himchan OH ,  Seong-Mok CHO ,  Sung Haeng CHO ,  Ji Hun CHOI ,  Jae-Eun PI ,  Chi-Sun HWANG

IPC: H01L27/32 ,  G09G3/3266 ,  G09G3/3225

Abstract: Provided are a semiconductor device, a display panel, and a display device including the same. The semiconductor device includes a lower electrode on one side of a substrate, a spacer on another side of the substrate, a middle electrode on the spacer, a lower channel layer on portions of a sidewall of the spacer, the middle electrode, and the lower electrode, a lower gate insulating layer on the lower channel layer, a common gate electrode on the gate insulating layer, an upper gate insulating layer on the common gate electrode, an upper electrode on the spacer and the upper gate insulating layer of the middle electrode, an upper channel layer connected to the upper electrode and disposed on a sidewall of the upper gate insulating layer, and a contact electrode connected to a portion of the upper channel layer and passing through the lower gate insulating layer and the upper gate insulating layer outside the common gate electrode so as to be connected to the lower electrode.

公开(公告)号：US20250098218A1

公开(公告)日：2025-03-20

申请号：US18762381

申请日：2024-07-02

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jae-Eun PI ,  Seung Youl KANG ,  Yong Hae KIM ,  Joo Yeon KIM ,  Hee-ok KIM ,  Jaehyun MOON ,  Jong-Heon YANG ,  Himchan OH ,  Seong-Mok CHO ,  Ji Hun CHOI ,  Chi-Sun HWANG

IPC: H01L29/417 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786

Abstract: A thin film transistor includes a first gate electrode on a substrate, a gate insulating film on the first gate electrode, a first active layer on the gate insulating film, a drain electrode on one side of the first active layer, a sidewall spacer on a side wall of the drain electrode, and a first source electrode provided on the other side of the first active layer and a sidewall of the sidewall spacer.