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公开(公告)号：US20180145671A1
公开(公告)日：2018-05-24
申请号：US15725905
申请日：2017-10-05
Inventor： Woojoo LEE , Jae-Jin LEE , Sukho LEE , Kyuseung HAN , Sang Pil KIM , Young Hwan BAE
IPC: H03K5/134
CPC classification number: H03K5/134 , H03K2005/00143
Abstract: Provided is a semiconductor device including a target circuit, a monitoring circuit, and a voltage controller. The target circuit includes a transistor. The monitoring circuit is configured to measure a temperature of the target circuit or measure a delay time between an input and an output of the target circuit. The voltage controller is configured to adjust a driving voltage for driving the target circuit or a back-bias voltage for adjusting a threshold voltage of the transistor by referring to at least one of the temperature and the delay time. As the temperature increases, the delay time decreases.
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公开(公告)号：US20170257632A1
公开(公告)日：2017-09-07
申请号：US15232542
申请日：2016-08-09
Inventor： Sukho LEE , Kyung Jin BYUN , Nak Woong EUM
IPC: H04N19/159 , H04N19/182 , H04N19/96 , H04N19/61 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/122
CPC classification number: H04N19/159 , H04N19/11 , H04N19/122 , H04N19/124 , H04N19/13 , H04N19/176 , H04N19/182 , H04N19/463 , H04N19/61 , H04N19/96
Abstract: Provided is an encoding method of an image encoding device including predicting an intra mode for coding blocks of a minimum size for intra prediction to generate an intra pixel; and using the intra mode of the coding blocks of the minimum size to restore an intra mode of coding blocks of a larger size.
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公开(公告)号：US20170347150A1
公开(公告)日：2017-11-30
申请号：US15586742
申请日：2017-05-04
Inventor： Woojoo LEE , Sukho LEE , Kyung Jin BYUN , Sung Weon KANG
IPC: H04N21/443 , H04N21/234 , H04N21/45 , H04N21/61
CPC classification number: H04N21/4436 , H04N21/23418 , H04N21/23614 , H04N21/44 , H04N21/4516 , H04N21/6125
Abstract: Provided is a video providing system. The video providing system includes a memory configured to store device information of a display device, an analyzer configured to receive an original video from the outside and analyze images in the original video, and a processor configured to generate, from the original video, video streams according to a streaming mode and control signals of the display device respectively corresponding to the video streams, based on device information of a display device and analysis information from the analyzer, and provide the video streams and the control signals to the display device.
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公开(公告)号：US20220201611A1
公开(公告)日：2022-06-23
申请号：US17552766
申请日：2021-12-16
Inventor： Hyuk KIM , HYUNG-IL PARK , Tae Wook KANG , Sung Eun KIM , Mi Jeong PARK , Kyung Jin BYUN , KWANG IL OH , Sukho LEE , Jae-Jin LEE , In Gi LIM , Kyuseung HAN
Abstract: Disclosed is an operating method of a user communication device, which includes receiving a wakeup signal from a stationary communication device over a first human body communication channel, the wakeup signal having a frequency in a low frequency band, switching from a standby mode to a wakeup mode in response to the wakeup signal, and receiving a data signal from the stationary communication device over the first human body communication channel during the wakeup mode, and the first human body communication channel is provided by a body of a user of the user communication device.
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公开(公告)号：US20190245532A1
公开(公告)日：2019-08-08
申请号：US16262738
申请日：2019-01-30
Inventor： Tae Wook KANG , Jae-Jin LEE , Kwang IL OH , Sung Eun KIM , Sukho LEE , Kyuseung HAN
CPC classification number: H03K17/145 , H03K17/08 , H03K2017/0806 , H03K2217/0027
Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.
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Patent Agency Ranking
公开(公告)号：US20240036817A1
公开(公告)日：2024-02-01
申请号：US18362596
申请日：2023-07-31
Inventor： Kyuseung HAN , Kyung Jin BYUN , Sukho LEE , Jae-Jin LEE
IPC: G06F5/01 , G06F15/78 , G06F1/3234
CPC classification number: G06F5/012 , G06F15/7807 , G06F1/3234
Abstract: Disclosed is an SoC including a CPU that generates a first function signal including a first command for a first soft float function while not having a floating point operation function, a system bus, and a soft float function circuit that receives the first function signal from the CPU through the system bus, and performs a first floating point operation corresponding to the first soft float function based on the first command.
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公开(公告)号：US20220109808A1
公开(公告)日：2022-04-07
申请号：US17399603
申请日：2021-08-11
Inventor： Sukho LEE , Sang Pil KIM , Young Hwan BAE , Jae-Jin LEE , Kyuseung HAN , Tae Wook KANG , Sung Eun KIM , Hyuk KIM , Kyung Hwan PARK , Hyung-IL PARK , Kyung Jin BYUN , Kwang IL OH , In Gi LIM
Abstract: Disclosed is a network-on-chip including a first data converter that receives first image data and second image data from at least one image sensor and encodes one image data among the first image data and the second image data, into first data, based on whether the first image data is identical to the second image data and a second data converter that receives non-image data from at least one non-image sensor and encodes the received non-image data into second data. The network-on-chip outputs the first data and the second data to transmit the first data and the second data to an external server at a burst length.
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公开(公告)号：US20210182462A1
公开(公告)日：2021-06-17
申请号：US17116637
申请日：2020-12-09
Inventor： Kyuseung HAN , Sukho LEE , Jae-Jin LEE
IPC: G06F30/331 , G06F13/12
Abstract: Disclosed is a method of operating a system-on-chip automatic design device. The system-on-chip automatic design device includes a first synthesizer and a second synthesizer. The method includes generating a first code, based on information of a first signal and information of a second signal that are used in a first IP (Intellectual Property) block, classifying a first signal code corresponding to the first signal and a second signal code corresponding to the second signal from the first code, synthesizing, through the first synthesizer, a first communication architecture configured to transmit the first signal, based on the classified first signal code, and synthesizing, through the second synthesizer, a second communication architecture configured to transmit the second signal based on the classified second signal code.
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公开(公告)号：US20200092226A1
公开(公告)日：2020-03-19
申请号：US16556905
申请日：2019-08-30
Inventor： Kyuseung HAN , Sukho LEE , Jae-Jin LEE , Sang Pil KIM , Young Hwan BAE , Kyung Jin BYUN
IPC: H04L12/933 , H04L12/42
Abstract: Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
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公开(公告)号：US20190286606A1
公开(公告)日：2019-09-19
申请号：US16265598
申请日：2019-02-01
Inventor： Kyuseung HAN , Hyeong Uk JANG , Sukho LEE , Jae-Jin LEE
IPC: G06F13/42
Abstract: Provided is a computing device. The computing device includes electronic circuits, and a network-on-chip configured to provide a communication channel between the electronic circuits. One of the electronic circuits is a processor. The network-on-chip includes a memory management unit for supporting a use of a virtual memory address of the processor.
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