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1.发明申请公开(公告)号：US20140167782A1
公开(公告)日：2014-06-19
申请号：US14027573
申请日：2013-09-16
Inventor： Soon Il Yeo
IPC: G01R29/26
CPC classification number: G01R31/002 , G01R29/0814 , G01R29/0835 , G01R31/001
Abstract: Provided is an electromagnetic interference (EMI) measuring device. The EMI measuring device according to the present invention includes an electromagnetic wave eliminating unit eliminating remaining electromagnetic waves from a DUT in response to an eliminating control signal of the control unit. The control unit may calculate EMI of the DUT on the basis of a measured result measured before the elimination of remaining electromagnetic waves. The EMI measuring device according to the present invention may compensate for an error due to remaining electromagnetic waves and measure EMI at high accuracy.
Abstract translation: 提供电磁干扰（EMI）测量装置。 根据本发明的EMI测量装置包括电磁波消除单元，其响应于控制单元的消除控制信号来消除来自DUT的剩余电磁波。 控制单元可以基于在消除剩余电磁波之前测量的测量结果来计算DUT的EMI。 根据本发明的EMI测量装置可以补偿由于剩余电磁波引起的误差并以高精度测量EMI。
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Patent Agency Ranking
公开(公告)号：US08697491B2
公开(公告)日：2014-04-15
申请号：US13653068
申请日：2012-10-16
Inventor： Woojin Chang , Soon Il Yeo , Hae Cheon Kim , Eun Soo Nam
IPC: H01L23/053 , H01L21/44
CPC classification number: H01L23/5389 , H01L23/3107 , H01L24/83 , H01L24/90 , H01L25/03 , H01L2224/90 , H01L2924/00011 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2224/83851 , H01L2924/00
Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.
Abstract translation: 提供半导体封装。 半导体封装包括封装体，多个半导体芯片和外部连接端子。 封装体与设置有导电图案和通孔的多个片层叠。 多个半导体芯片被插入到从封装主体的一个表面延伸的插入槽中。 外部连接端子设置在与封装主体的一个表面相对的另一表面上。 这里，多个半导体芯片电连接到外部连接端子。
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3.发明授权公开(公告)号：US09642292B2
公开(公告)日：2017-05-02
申请号：US14452043
申请日：2014-08-05
Inventor： Soon Il Yeo
CPC classification number: H05K9/0071 , H02J50/00 , H02J50/70
Abstract: Provided is an electromagnetic wave reduction apparatus for reducing an electromagnetic wave generated from a thermoelectric element. The electromagnetic wave reduction apparatus according to the present invention includes an electromagnetic wave sensing unit connected to a thermoelectric element and sensing an electromagnetic wave, an electromagnetic wave detecting unit detecting whether the sensed electromagnetic wave is greater than a reference value, an electromagnetic wave reduction circuit unit reducing the electromagnetic wave in response to an electromagnetic wave reduction control signal, and a circuit operation control unit generating the electromagnetic wave reduction control signal according to the detection result.
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4.发明授权公开(公告)号：US09494633B2
公开(公告)日：2016-11-15
申请号：US14027573
申请日：2013-09-16
Inventor： Soon Il Yeo
CPC classification number: G01R31/002 , G01R29/0814 , G01R29/0835 , G01R31/001
Abstract: Provided is an electromagnetic interference (EMI) measuring device. The EMI measuring device according to the present invention includes an electromagnetic wave eliminating unit eliminating remaining electromagnetic waves from a DUT in response to an eliminating control signal of the control unit. The control unit may calculate EMI of the DUT on the basis of a measured result measured before the elimination of remaining electromagnetic waves. The EMI measuring device according to the present invention may compensate for an error due to remaining electromagnetic waves and measure EMI at high accuracy.
Abstract translation: 提供电磁干扰（EMI）测量装置。 根据本发明的EMI测量装置包括电磁波消除单元，其响应于控制单元的消除控制信号来消除来自DUT的剩余电磁波。 控制单元可以基于在消除剩余电磁波之前测量的测量结果来计算DUT的EMI。 根据本发明的EMI测量装置可以补偿由于剩余电磁波引起的误差并以高精度测量EMI。
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5.发明授权Jig for measuring EMC of semiconductor chip and method for measuring EMC of semiconductor chip using the same 有权用于测量半导体芯片的EMC的夹具以及使用其测量半导体芯片的EMC的方法公开(公告)号：US09035660B2
公开(公告)日：2015-05-19
申请号：US13672858
申请日：2012-11-09
Inventor： Soon Il Yeo
CPC classification number: G01R1/04 , G01R1/0408 , G01R27/28 , G01R31/002
Abstract: Disclosed are a jig for measuring EMC of a semiconductor chip and a method for measuring EMC that can accurately measure the EMC at a semiconductor chip level. The jig for measuring EMC of a semiconductor chip according to the exemplary embodiment of the present disclosure includes: a chip mount unit on which the semiconductor chip for which the EMC is to be measured is mounted; a memory unit configured to store EMC information of components in a system in which the semiconductor chip is used; and a measurement control unit configured to extract the EMC information stored in the memory unit and provide the extracted EMC information to the chip mount unit at the time of measuring the EMC of the semiconductor chip.
Abstract translation: 公开了用于测量半导体芯片的EMC的夹具和用于测量半导体芯片级的EMC的电磁兼容性的方法。 根据本公开的示例性实施例的用于测量半导体芯片的EMC的夹具包括：安装有要测量EMC的半导体芯片的芯片安装单元; 存储器单元，被配置为将组件的EMC信息存储在其中使用半导体芯片的系统中; 以及测量控制单元，被配置为在测量半导体芯片的EMC时提取存储在存储单元中的EMC信息并将提取的EMC信息提供给芯片安装单元。
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公开(公告)号：US08683397B2
公开(公告)日：2014-03-25
申请号：US13674281
申请日：2012-11-12
Inventor： Soon Il Yeo , Young Ho Kim
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F2217/66 , G06F2217/82
Abstract: Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP.
Abstract translation: 公开了一种设计半导体芯片的方法和设备。 所公开的方法包括以下步骤：存储多个EMS（电磁敏感性）半导体IP（知识产权）和多个EMI（电磁干扰）半导体IP; 在输入引脚的情况下，从多个EMS屏蔽半导体IP中选择适当的半导体IP，并且在输出引脚的情况下从多个EMI屏蔽半导体IP中选择合适的半导体IP; 以及通过配置所选择的半导体IP来设计半导体芯片。
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