-
公开(公告)号：US09825622B2
公开(公告)日：2017-11-21
申请号：US15217271
申请日：2016-07-22
Inventor： Woojin Chang , Sang Choon Ko , Jae Kyoung Mun , Young Rak Park
IPC: H03K17/687 , H03K17/081 , H03K17/74
CPC classification number: H03K17/08104 , H03K17/0822 , H03K17/74
Abstract: A cascode switch circuit includes a first transistor, a second transistor, and a protector. A first transistor receives a signal from a first terminal through a first end and transfers the signal to a second end in response to a first control signal. A second transistor delivers the signal that the first transistor transfers to a second terminal in response to a second control signal. A protector is connected between a gate of the first transistor and the second terminal. The first control signal is provided to allow the first transistor to operate in a normally-on state. The second control signal is provided to allow the second transistor to operate in a normally-off state.
-
公开(公告)号：US09666569B2
公开(公告)日：2017-05-30
申请号：US14815378
申请日：2015-07-31
Inventor： Woojin Chang
IPC: H01L25/18 , H01L23/492 , H01L27/108 , H01L29/94 , H01L29/66 , H01L25/07 , H01L23/00 , H01L23/495 , H01L23/498
CPC classification number: H01L25/18 , H01L23/492 , H01L23/49562 , H01L23/49575 , H01L23/49844 , H01L24/48 , H01L24/49 , H01L25/072 , H01L2224/48137 , H01L2224/48177 , H01L2924/00014 , H01L2924/1033 , H01L2924/13091 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.
-
公开(公告)号：US08697491B2
公开(公告)日：2014-04-15
申请号：US13653068
申请日：2012-10-16
Inventor： Woojin Chang , Soon Il Yeo , Hae Cheon Kim , Eun Soo Nam
IPC: H01L23/053 , H01L21/44
CPC classification number: H01L23/5389 , H01L23/3107 , H01L24/83 , H01L24/90 , H01L25/03 , H01L2224/90 , H01L2924/00011 , H01L2924/01079 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2224/83851 , H01L2924/00
Abstract: A semiconductor package is provided. The semiconductor package includes a package body, a plurality of semiconductor chips, and an external connection terminal. The package body is stacked with a plurality of sheets where conductive patterns and vias are disposed. The plurality of semiconductor chips are inserted into insert slots extending from one surface of the package body. The external connection terminal is provided on other surface opposite to the one surface of the package body. Here, the plurality of semiconductor chips are electrically connected to the external connection terminal.
Abstract translation: 提供半导体封装。 半导体封装包括封装体，多个半导体芯片和外部连接端子。 封装体与设置有导电图案和通孔的多个片层叠。 多个半导体芯片被插入到从封装主体的一个表面延伸的插入槽中。 外部连接端子设置在与封装主体的一个表面相对的另一表面上。 这里，多个半导体芯片电连接到外部连接端子。
-
公开(公告)号：US10020201B2
公开(公告)日：2018-07-10
申请号：US15093814
申请日：2016-04-08
Inventor： Chi Hoon Jun , Sang Choon Ko , Seok-Hwan Moon , Woojin Chang , Sung-Bum Bae , Young Rak Park , Je Ho Na , Jae Kyoung Mun , Eun Soo Nam
IPC: H01L23/367 , H01L21/3065 , H01L21/308 , H01L21/3205 , H01L23/473 , H01L23/467
CPC classification number: H01L21/3065 , H01L21/3081 , H01L21/32051 , H01L23/367 , H01L23/467 , H01L23/473 , H01L2924/0002 , H01L2924/00
Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.
-
公开(公告)号：US09159583B2
公开(公告)日：2015-10-13
申请号：US14310784
申请日：2014-06-20
Inventor： Sang Choon Ko , Jae Kyoung Mun , Woojin Chang , Sung-Bum Bae , Young Rak Park , Chi Hoon Jun , Seok-Hwan Moon , Woo-Young Jang , Jeong-Jin Kim , Hyungyu Jang , Je Ho Na , Eun Soo Nam
IPC: H01L21/33 , H01L21/321 , H01L21/02 , H01L21/283
CPC classification number: H01L21/3212 , H01L21/0254 , H01L21/283 , H01L21/28575 , H01L21/28581 , H01L29/2003 , H01L29/41766 , H01L29/452 , H01L29/66462 , H01L29/7786
Abstract: Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer.
Abstract translation: 提供一种制造氮化物半导体器件的方法。 该方法包括在生长衬底上形成多个电极，在其上依次层叠有第一和第二氮化物半导体层，分别在多个电极上形成上部金属层，去除生长衬底以暴露第一氮化物半导体层的下表面 并且在第一氮化物半导体层的暴露的下表面上顺序地形成第三氮化物半导体层和下金属层。
-
Patent Agency Ranking
公开(公告)号：US09136347B2
公开(公告)日：2015-09-15
申请号：US14311675
申请日：2014-06-23
Inventor： Young Rak Park , Sang Choon Ko , Woojin Chang , Jae Kyoung Mun , Sung-Bum Bae
IPC: H01L29/66 , H01L29/20 , H01L29/205 , H01L29/49 , H01L29/417 , H01L29/778 , H01L29/737
CPC classification number: H01L29/66462 , H01L29/2003 , H01L29/4175 , H01L29/41758 , H01L29/4236 , H01L29/66431 , H01L29/737 , H01L29/778 , H01L29/7786
Abstract: Provided is a nitride semiconductor device including: a substrate having through via holes; first and second nitride semiconductor layers sequentially stacked on the substrate; drain electrodes and source electrodes provided on the second nitride semiconductor layer; and an insulating pattern provided on the second nitride semiconductor layer, the insulating pattern having upper via holes provided on the drain electrodes, wherein the through via holes are extended into the first and second nitride semiconductor layers and expose a bottom of each of the source electrodes.
Abstract translation: 提供一种氮化物半导体器件，包括：具有通孔的衬底; 顺序堆叠在基板上的第一和第二氮化物半导体层; 设置在第二氮化物半导体层上的漏电极和源电极; 以及设置在所述第二氮化物半导体层上的绝缘图案，所述绝缘图案具有设置在所述漏电极上的上通孔，所述贯通通孔延伸到所述第一氮化物半导体层和所述第二氮化物半导体层中，并暴露出每个所述源电极的底部 。
-
公开(公告)号：US11817826B2
公开(公告)日：2023-11-14
申请号：US17886061
申请日：2022-08-11
Inventor： Woojin Chang , Dong Min Kang , Byoung-Gue Min , Jong Yul Park , Jongmin Lee , Yoo Jin Jang , Kyu Jun Cho , Hong Gu Ji
Abstract: Disclosed is a frequency mixer. The frequency mixer includes a first matching circuit that generates a matched local oscillator (LO) signal based on an LO signal, a non-linear circuit that generates a non-linear LO signal based on the matched LO signal, a second matching circuit that generates a matched radio frequency (RF) signal based on an RF signal, a mixing circuit that generates a mixed signal based on a mixing of the non-linear LO signal and the matched RF signal, a third matching circuit that generates an intermediate frequency (IF) signal based on the mixed signal, wherein the non-linear circuit includes a non-linear transistor, a bias transistor, and an internal matching circuit connected in series.
-
公开(公告)号：US11223333B2
公开(公告)日：2022-01-11
申请号：US16941691
申请日：2020-07-29
Inventor： Woojin Chang , Seong-Il Kim , Sang-Heung Lee , Jongmin Lee
Abstract: Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.
-
公开(公告)号：US08633057B2
公开(公告)日：2014-01-21
申请号：US13875795
申请日：2013-05-02
Inventor： Woojin Chang
IPC: H01L21/50
CPC classification number: H01L21/50 , H01L23/49805 , H01L23/5389 , H01L24/24 , H01L24/25 , H01L24/73 , H01L24/82 , H01L25/0652 , H01L25/16 , H01L2224/24147 , H01L2224/24195 , H01L2224/73259 , H01L2224/76155 , H01L2224/82102 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/07802 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/00
Abstract: Provided is a semiconductor package and a method of fabricating the same. The semiconductor package includes: a package body including a plurality of sheets; semiconductor chips mounted in the package body; and an external connection terminal provided on a first side of the package body, wherein the sheets are stacked in a parallel direction to the first side.
Abstract translation: 提供一种半导体封装及其制造方法。 半导体封装包括：包括多个片的封装体; 半导体芯片安装在封装体内; 以及设置在所述封装主体的第一侧上的外部连接端子，其中所述片材沿与所述第一侧平行的方向堆叠。
-
公开(公告)号：US10256811B2
公开(公告)日：2019-04-09
申请号：US15654792
申请日：2017-07-20
Inventor： Woojin Chang , Jong-Won Lim , Dong Min Kang , Dong-Young Kim , Seong-il Kim , Hae Cheon Kim , Jae Won Do , Byoung-Gue Min , Min Jeong Shin , Hokyun Ahn , Hyung Sup Yoon , Sang-Heung Lee , Jongmin Lee , Sungjae Chang , Yoo Jin Jang , Hyunwook Jung , Kyu Jun Cho , Hong Gu Ji
IPC: H03K17/687 , H03K17/693 , G11C5/14 , H03K19/0175 , H03K3/353 , H03K17/0812 , H03K17/10 , H03K17/12 , H03K17/14 , H03K17/16 , H03K17/28
Abstract: Provided is a cascode circuit including first and second transistors connected between a drain terminal and a source terminal in cascode form, a level sifter configured to change a voltage level of a switching control signal applied to a gate terminal and provide the changed switching control signal to a gate of the first transistor, a buffer configured to delay the switching control signal and provide the delayed switching control signal to a gate of the second transistor, and a first resistor connected between the level shifter and the gate of the first transistor.
-
-
-
-
-
-
-
-
-
Search Results
13
records
(took 0.016 seconds)
