公开(公告)号：US08977139B2

公开(公告)日：2015-03-10

申请号：US13663056

申请日：2012-10-29

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'linh Nguyen

IPC: H04B10/69

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

公开(公告)号：US10361687B2

公开(公告)日：2019-07-23

申请号：US15847842

申请日：2017-12-19

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  The'linh Nguyen ,  Timothy G. Moran

IPC: G01F1/10 ,  G01F1/58 ,  G01F1/60 ,  G06F1/10 ,  H03K5/00 ,  H03K5/02 ,  H04L7/00 ,  H04L7/04 ,  G01F15/06 ,  G01F25/00

Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

公开(公告)号：US09847776B2

公开(公告)日：2017-12-19

申请号：US14330987

申请日：2014-07-14

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  The'linh Nguyen ,  Timothy G. Moran

IPC: H03K5/00 ,  H03K5/02 ,  H04L7/00 ,  G06F1/10 ,  H04L7/04

CPC classification number: H03K5/00006 ,  G06F1/10 ,  H03K5/02 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/04

Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

公开(公告)号：US08912827B2

公开(公告)日：2014-12-16

申请号：US13774817

申请日：2013-02-22

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  Jason Y. Miao ,  The'linh Nguyen

IPC: H03K3/00 ,  G05F1/625 ,  H03K19/0175

CPC classification number: G05F1/625 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017527

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

Abstract translation: 电路可以包括被配置为接收信号的输入节点和被配置为耦合到负载的输出节点。 电路还可以包括耦合在输入节点和输出节点之间的第一电路。 第一电路可以被配置为接收信号并以第一电压驱动输出节点上的信号。 电路还可以包括耦合到输出节点的有源器件和耦合到有源器件和输入节点的第二电路。 第二电路可以被配置为接收信号并且以第二电压将信号驱动到有源器件。 电路还可以包括抽头电路，其被配置为在由第二电路驱动的信号到达有源器件之前，将信号的修改版本选择性地应用于由第二电路驱动的信号。