公开(公告)号：US09148129B2

公开(公告)日：2015-09-29

申请号：US13912945

申请日：2013-06-07

Applicant: Finisar Corporation

Inventor： Jason Miao ,  Arik Zafrany ,  Georgios Kalogerakis

IPC: H03B1/00 ,  H03K3/00 ,  H03K3/01 ,  H03K5/12 ,  H03K5/156 ,  H03K19/003

CPC classification number: H03K3/01 ,  H03K5/12 ,  H03K5/1565 ,  H03K19/00323

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.

Abstract translation: 电路可以包括被配置为接收信号的输入节点和被配置为耦合到负载的输出节点。 电路还可以包括耦合在输入节点和输出节点之间的第一电路，第一电路被配置为接收信号并以第一电压驱动输出节点上的信号。 电路还可以包括被配置为调节由第一电路驱动的信号的电流的信号调整电路。 信号调整电路可以被配置为施加第一电流调整以在信号的下降沿或信号的上升沿中的一个但不是两个信号处调整信号的电流。

公开(公告)号：US10361687B2

公开(公告)日：2019-07-23

申请号：US15847842

申请日：2017-12-19

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  The'linh Nguyen ,  Timothy G. Moran

IPC: G01F1/10 ,  G01F1/58 ,  G01F1/60 ,  G06F1/10 ,  H03K5/00 ,  H03K5/02 ,  H04L7/00 ,  H04L7/04 ,  G01F15/06 ,  G01F25/00

Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

公开(公告)号：US09847776B2

公开(公告)日：2017-12-19

申请号：US14330987

申请日：2014-07-14

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  The'linh Nguyen ,  Timothy G. Moran

IPC: H03K5/00 ,  H03K5/02 ,  H04L7/00 ,  G06F1/10 ,  H04L7/04

CPC classification number: H03K5/00006 ,  G06F1/10 ,  H03K5/02 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/04

Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

公开(公告)号：US09407259B2

公开(公告)日：2016-08-02

申请号：US14317190

申请日：2014-06-27

Applicant: FINISAR CORPORATION

Inventor： Arik Zafrany ,  Georgios Kalogerakis

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  H03F3/45 ,  H01S5/042 ,  H04B10/50

CPC classification number: H03K17/6871 ,  H01S5/042 ,  H01S5/0427 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45282 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45554 ,  H03F2203/45562 ,  H03F2203/45598 ,  H03F2203/45702 ,  H04B10/502 ,  H04B10/503

Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.

Abstract translation: 电路可以包括第一和第二输入节点，第一和第二输出节点，第一和第二中间节点，第一和第二电阻，耦合到第一输入节点的第一放大晶体管，第一电阻和第一中间节点， 耦合到第二输入节点的放大晶体管，第二电阻和第二中间节点。 电路还可以包括耦合到第一输出节点和第一中间节点的第一有源器件，耦合到第二输出节点和第二中间节点的第二有源器件，耦合到第一输出节点的第一有效器件， 基于第二中间节点上的第二中间信号的行为，以及耦合到第二输出节点并被配置为基于第一中间节点上的第一中间信号进行的第二输出晶体管。

公开(公告)号：US09191123B2

公开(公告)日：2015-11-17

申请号：US14642651

申请日：2015-03-09

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'Linh Nguyen

IPC: H04B10/69 ,  H04B10/61

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Abstract translation: 电路可以包括被配置为接收光信号并将光信号转换成电流信号的光电二极管。 电路还可以包括耦合到光电二极管并被配置为将电流信号转换成电压信号的跨阻放大器。 电路还可以包括耦合到跨阻放大器的均衡器，并且被配置为使电压信号均衡以至少部分地补偿光信号的高频分量的损耗。 均衡器和跨阻放大器可以容纳在单个集成电路内。

公开(公告)号：US09146367B2

公开(公告)日：2015-09-29

申请号：US13706454

申请日：2012-12-06

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  The'Linh Nguyen ,  Jason Miao

IPC: G02B6/42 ,  G02B6/43 ,  H04B10/50

CPC classification number: G02B6/4246 ,  G02B6/4249 ,  G02B6/428 ,  G02B6/43 ,  H04B10/50 ,  Y10T29/49002

Abstract: A modular device for an optical communication module configured to be coupled to an optical transmission medium. The modular device may include a first edge and a second edge and N number of electrical circuit channels between the first and second edges. Each electrical circuit channel may include at least one element configured to provide functionality for communicating optical signals through the optical transmission medium. The modular device may also have a width between the first and second edges so that each of the N number of electrical circuit channels of C number of modular devices aligns with one of P number of interface channels of an opto-electrical interface configured to be coupled to the optical transmission medium when C equals P/N and C is a whole number greater than zero.

Abstract translation: 一种用于光通信模块的模块化设备，其被配置为耦合到光传输介质。 模块化装置可以包括在第一和第二边缘之间的第一边缘和第二边缘以及N个电路通道。 每个电路通道可以包括配置成提供通过光传输介质传送光信号的功能的至少一个元件。 模块化设备还可以具有第一和第二边缘之间的宽度，使得C个模块化设备的N个电路通道中的每一个与光电接口的P个接口通道中的一个对准，该光电接口的接口通道被配置为被耦合 当C等于P / N并且C是大于零的整数时，到光传输介质。

公开(公告)号：US20150180587A1

公开(公告)日：2015-06-25

申请号：US14642651

申请日：2015-03-09

Applicant: FINISAR CORPORATION

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'Linh Nguyen

IPC: H04B10/61

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

Abstract translation: 电路可以包括被配置为接收光信号并将光信号转换成电流信号的光电二极管。 电路还可以包括耦合到光电二极管并被配置为将电流信号转换成电压信号的跨阻放大器。 电路还可以包括耦合到跨阻放大器的均衡器，并且被配置为使电压信号均衡以至少部分地补偿光信号的高频分量的损耗。 均衡器和跨阻放大器可以容纳在单个集成电路内。

公开(公告)号：US08977139B2

公开(公告)日：2015-03-10

申请号：US13663056

申请日：2012-10-29

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  Lionel Li ,  The'linh Nguyen

IPC: H04B10/69

CPC classification number: H04B10/616 ,  H04B10/6971

Abstract: A circuit may include a photodiode configured to receive an optical signal and convert the optical signal to a current signal. The circuit may also include a transimpedance amplifier coupled to the photodiode and configured to convert the current signal to a voltage signal. The circuit may also include an equalizer coupled to the transimpedance amplifier and configured to equalize the voltage signal to at least partially compensate for a loss of a high frequency component of the optical signal. The equalizer and the transimpedance amplifier may be housed within a single integrated circuit.

公开(公告)号：US09673815B2

公开(公告)日：2017-06-06

申请号：US15225711

申请日：2016-08-01

Applicant: FINISAR CORPORATION

Inventor： Arik Zafrany ,  Georgios Kalogerakis

IPC: H03B1/00 ,  H03K3/00 ,  H03K17/687 ,  H03F3/45 ,  H04B10/50

CPC classification number: H03K17/6871 ,  H01S5/042 ,  H01S5/0427 ,  H03F3/45085 ,  H03F3/45179 ,  H03F3/45282 ,  H03F2203/45288 ,  H03F2203/45301 ,  H03F2203/45554 ,  H03F2203/45562 ,  H03F2203/45598 ,  H03F2203/45702 ,  H04B10/502 ,  H04B10/503

Abstract: A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.

公开(公告)号：US08912827B2

公开(公告)日：2014-12-16

申请号：US13774817

申请日：2013-02-22

Applicant: Finisar Corporation

Inventor： Georgios Kalogerakis ,  Jason Y. Miao ,  The'linh Nguyen

IPC: H03K3/00 ,  G05F1/625 ,  H03K19/0175

CPC classification number: G05F1/625 ,  H03K19/00361 ,  H03K19/017509 ,  H03K19/017527

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

Abstract translation: 电路可以包括被配置为接收信号的输入节点和被配置为耦合到负载的输出节点。 电路还可以包括耦合在输入节点和输出节点之间的第一电路。 第一电路可以被配置为接收信号并以第一电压驱动输出节点上的信号。 电路还可以包括耦合到输出节点的有源器件和耦合到有源器件和输入节点的第二电路。 第二电路可以被配置为接收信号并且以第二电压将信号驱动到有源器件。 电路还可以包括抽头电路，其被配置为在由第二电路驱动的信号到达有源器件之前，将信号的修改版本选择性地应用于由第二电路驱动的信号。