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1.发明授权Semiconductor integrated circuit device having clock buffers and method for arranging the clock buffers on the device 有权具有时钟缓冲器的半导体集成电路器件和用于在器件上布置时钟缓冲器的方法公开(公告)号：US07685552B2
公开(公告)日：2010-03-23
申请号：US11690985
申请日：2007-03-26
申请人： Fujio Ishihara , Ryubi Okuda , Toshihiko Himeno , Hiroshige Fujii
发明人： Fujio Ishihara , Ryubi Okuda , Toshihiko Himeno , Hiroshige Fujii
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/62 , G06F2217/84
摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.
摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。
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公开(公告)号：US20070240087A1
公开(公告)日：2007-10-11
申请号：US11690985
申请日：2007-03-26
申请人： Fujio ISHIHARA , Ryubi Okuda , Toshihiko Himeno , Hiroshige Fujii
发明人： Fujio ISHIHARA , Ryubi Okuda , Toshihiko Himeno , Hiroshige Fujii
CPC分类号： G06F17/5045 , G06F2217/62 , G06F2217/84
摘要： This invention concerns a semiconductor integrated circuit device comprising a plurality of circuit elements arranged in a chip and operating in response to a same clock signal; clock buffers arranged at intersecting points decided based on positions of the plurality of circuit elements, the intersecting points being included in intersecting points of a pseudo mesh virtually assumed to cover up a region in the chip including the plurality of circuit elements; and a main wiring transmitting the clock signal to the clock buffers.
摘要翻译： 本发明涉及一种半导体集成电路器件，其包括布置在芯片中并响应于相同时钟信号而工作的多个电路元件; 布置在基于多个电路元件的位置确定的相交点处的时钟缓冲器，所述交点包括在虚拟网格的相交点中，虚拟地假定为覆盖包括多个电路元件的芯片中的区域; 以及将时钟信号发送到时钟缓冲器的主线。
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公开(公告)号：US07619921B2
公开(公告)日：2009-11-17
申请号：US11530551
申请日：2006-09-11
IPC分类号： G11C16/06
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译： 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。
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公开(公告)号：US07313022B2
公开(公告)日：2007-12-25
申请号：US11032165
申请日：2005-01-11
申请人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
发明人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
IPC分类号： G11C16/04
CPC分类号： G11C16/20
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.
摘要翻译： 非易失性半导体存储器件包括具有多个非易失性存储器单元的存储单元阵列，被配置为将地址数据作为其输入解码以从存储单元阵列中选择存储单元的解码电路，以及配置为 以检测和放大存储单元阵列的选定存储单元的数据。 存储单元阵列包括具有初始设置数据和状态数据被编程在其中的初始设置数据区域。 初始设置数据用于确定存储器操作条件，并且状态数据指示初始设置数据区域是否在功能上当前正常。
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公开(公告)号：US6097638A
公开(公告)日：2000-08-01
申请号：US22014
申请日：1998-02-11
CPC分类号： G11C16/26
摘要： An EEPROM employs, as a scheme of detecting data of a memory cell in a memory cell array, a scheme of detecting the potential of a bit line potential sense node, which depends on the relationship in amplitude between the current for charging a bit line from a current source and the discharge current flowing to a selected cell using a sense amplifier. The sense amplifier is arranged in correspondence with one bit line and includes a constant current source transistor for charging the corresponding bit line, a latch circuit for latching memory cell data read out to the bit line potential sense node, and a switch transistor for turning on/off the charge path to the bit line based on data of the latch circuit. In the verify read mode, the cell current between the Vcc node and Vss node of a cell not to be written or a completely written cell can be turned off, so verification can be performed without flowing any unnecessary current.
摘要翻译： 作为检测存储单元阵列中的存储单元的数据的方案，EEPROM采用检测位线电位检测节点的电位的方案，该方案取决于用于对位线的充电电流之间的幅度的关系， 电流源和使用读出放大器流向选定单元的放电电流。 读出放大器与一个位线相对应地布置，并且包括用于对相应位线充电的恒流源晶体管，用于锁存读出到位线电位检测节点的存储单元数据的锁存电路和用于导通的开关晶体管 /根据锁存电路的数据关闭位线的充电路径。 在验证读取模式下，可以关闭不要写入的单元的Vcc节点和Vss节点之间的单元电流，或者完全写入单元的单元电流可以被关闭，因此可以在不流过任何不必要的电流的情况下执行验证。
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6.发明授权Method, system and apparatus for producing a clock with desired frequency characteristics 失效用于产生具有期望频率特性的时钟的方法，系统和装置公开(公告)号：US07421609B2
公开(公告)日：2008-09-02
申请号：US11181359
申请日：2005-07-14
申请人： Toshihiko Himeno
发明人： Toshihiko Himeno
IPC分类号： G06F1/04
摘要： Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.
摘要翻译： 公开了可以在保持时钟信号的最大频率的同时降低时钟信号的平均频率的电路的系统和方法。 这些系统和方法的实施例可以允许接收时钟信号的电路，并且可以输出具有平均接收时钟信号的频率的平均某个比率的频率的时钟信号，但仍具有基本相等的最大频率 到接收到的时钟信号的频率。 在一种操作模式中，这些电路可以输出与所接收的时钟信号基本相同的时钟信号，而在另一种操作模式下，这些电路可以在时间间隔期间输出与所接收的时钟基本相同的时钟信号，从而降低平均频率 输出时钟信号相对于所接收的时钟信号，同时保持接收到的时钟信号的最大频率。
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公开(公告)号：US20050125595A1
公开(公告)日：2005-06-09
申请号：US11032165
申请日：2005-01-11
申请人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
发明人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
CPC分类号： G11C16/20
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.
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公开(公告)号：US06646930B2
公开(公告)日：2003-11-11
申请号：US09968983
申请日：2001-10-03
申请人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
发明人： Ken Takeuchi , Tamio Ikehashi , Toshihiko Himeno
IPC分类号： G11C700
CPC分类号： G11C16/20
摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells, a decode circuit configured to decode address data as input thereto to select a memory cell from the memory cell array, and a data sense circuit configured to detect and amplify the data of the selected memory cell of the memory cell array. The memory cell array includes an initial setup data region with initial setup data and status data being programmed thereinto. The initial setup data is used for determination of memory operating conditions, and the status data indicates whether the initial setup data region is presently normal or not in functionality.
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公开(公告)号：US20070016816A1
公开(公告)日：2007-01-18
申请号：US11181359
申请日：2005-07-14
申请人： Toshihiko Himeno
发明人： Toshihiko Himeno
IPC分类号： G06F1/00
摘要： Systems and methods for circuits which can reduce the average frequency of a clock signal while keeping the maximum frequency of the clock signal are disclosed. Embodiments of these systems and methods may allow for a circuit which receives a clock signal and can output a clock signal with a frequency which is on average some ratio of the frequency of the received clock signal, but still has a maximum frequency which is substantially equal to the frequency of the received clock signal. In one mode of operation, these circuits may output a clock signal substantially identical to a received clock signal, while in another mode of operation these circuits may output a clock signal substantially identical to a received clock during a time interval, thus reducing the average frequency of the output clock signal with respect to the received clock signal while maintaining the maximum frequency of the received clock signal.
摘要翻译： 公开了可以在保持时钟信号的最大频率的同时降低时钟信号的平均频率的电路的系统和方法。 这些系统和方法的实施例可以允许接收时钟信号的电路，并且可以输出具有平均接收时钟信号的频率的平均某个比率的频率的时钟信号，但仍具有基本相等的最大频率 到接收到的时钟信号的频率。 在一种操作模式中，这些电路可以输出与所接收的时钟信号基本相同的时钟信号，而在另一种操作模式下，这些电路可以在时间间隔期间输出与所接收的时钟基本相同的时钟信号，从而降低平均频率 输出时钟信号相对于所接收的时钟信号，同时保持接收到的时钟信号的最大频率。
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公开(公告)号：US20070016738A1
公开(公告)日：2007-01-18
申请号：US11530551
申请日：2006-09-11
CPC分类号： G11C29/789 , G11C7/20 , G11C16/20 , G11C2029/4402
摘要： A non-volatile semiconductor memory includes a memory cell array having a plurality of electrically-rewritable non-volatile memory cells. The memory cell array is provided with an initially-setting data area, programmed in which is initially-setting data for deciding memory operation requirements. The non-volatile semiconductor memory also includes an initial-set data latch. The initially-setting data of the memory cell array is read out and transferred to the data latch in an initially-setting operation.
摘要翻译： 非易失性半导体存储器包括具有多个电可重写非易失性存储单元的存储单元阵列。 存储单元阵列设置有初始设置的数据区，其中编程有初始设置数据，用于决定存储器操作要求。 非易失性半导体存储器还包括初始设置数据锁存器。 在初始设置操作中，存储单元阵列的初始设置数据被读出并传送到数据锁存器。
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