公开(公告)号：US10460782B1

公开(公告)日：2019-10-29

申请号：US16055952

申请日：2018-08-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yentsai Huang

IPC: G11C11/00 ,  G11C11/16 ,  G06F11/07 ,  G11C13/00

Abstract: Integrated circuits including memory cells and methods for operating memory cells are provided. In an embodiment, a method is provided for operating a memory including a plurality of operational memory cells. The method includes providing a word line voltage on a selected word line corresponding to a selected operational memory cell of the plurality of operational memory cells and to a corresponding reference memory cell. The method includes applying an operational bias current on an operational bit line to the selected operational memory cell. Also, the method includes scanning a reference bias current from a first value to a second value on a reference bit line to the reference memory cell. Further, the method includes comparing reference cell currents on the reference bit line with an operational cell current on the operational bit line to determine a logic state of the selected operational memory cell.

公开(公告)号：US10706905B1

公开(公告)日：2020-07-07

申请号：US16234954

申请日：2018-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yentsai Huang ,  Chunsung Chiang ,  Wuyang Hao ,  Jack T. Wong ,  Lejan Pu

IPC: G11C11/00 ,  G11C11/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.

公开(公告)号：US10741255B1

公开(公告)日：2020-08-11

申请号：US16526196

申请日：2019-07-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yentsai Huang

IPC: G11C16/24 ,  G11C11/16

Abstract: A sense amplifier includes, among other components, a first capacitor adapted to be charged to a precharge voltage, a complementary transistor pair (adapted to connect to the first capacitor, to a reference resistance device, and to a memory cell), a comparator adapted to connect to the complementary transistor pair, and a second capacitor adapted to connect to the comparator. The complementary transistor pair is adapted to produce a first bit voltage based on the precharge voltage and the reference resistance of the reference resistance device. The comparator is adapted to charge the second capacitor to a comparison voltage based on the first bit voltage. The complementary transistor pair is adapted to produce a cell bit voltage based on the precharge voltage and the resistance of the memory cell. The comparator is adapted to compare the cell bit voltage to the comparison voltage to produce an amplified memory cell value.

公开(公告)号：US20200211610A1

公开(公告)日：2020-07-02

申请号：US16234954

申请日：2018-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yentsai Huang ,  Chunsung Chiang ,  Wuyang Hao ,  Jack T. Wong ,  Lejan Pu

IPC: G11C11/16

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to a single path memory sense amplifier circuit and methods of manufacture. The circuit includes a sense amplifier circuit comprising a plurality of self-aligned transistors in a single sensing path; and a memory array connected to the sense amplifier circuit by the single sensing path.

公开(公告)号：US10468082B1

公开(公告)日：2019-11-05

申请号：US16140417

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Yentsai Huang

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic random access memory (MRAM) sense amplifier circuit is provided that includes a pre-amplifier circuit that includes a data leg, a reference leg, and an operational amplifier. The data leg includes a first P-channel transistor and a first N-channel transistor that receives a local data bit bias voltage and outputs a data branch output voltage. The reference leg includes a second P-channel transistor and a second N-channel transistor. The transistors of the reference leg mismatch the transistors of the data leg due to device variations. The second N-channel transistor receives a global reference bit bias voltage, and outputs a reference voltage. The operational amplifier determines the difference between the data branch output voltage and the reference voltage, and generates an adjusted local data bit bias voltage that matches the global reference bit bias voltage to offset the mismatches that exist between the data leg and the reference leg.