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    LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON
    2.
    发明申请
    LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON 审中-公开
    多孔硅上的低缺陷III-V半导体模板

    公开(公告)号：US20160268123A1

    公开(公告)日：2016-09-15

    申请号：US14645449

    申请日：2015-03-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L21/02 ,  H01L29/16 ,  H01L29/207 ,  H01L29/10 ,  H01L29/36

    CPC classification number: H01L29/16 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02538 ,  H01L21/02658 ,  H01L29/36

    Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the III-V layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

    Abstract translation: 一种在多孔半导体结构上形成半导体的方法。 该方法可以包括形成堆叠，堆叠包括（从底部到顶部）衬底，基底硅层，厚硅层和薄硅层，其中薄硅层和厚硅层被松弛; 使用多孔化方法将厚硅层转化为多孔硅层; 在薄硅层上形成III-V层，III-V层被松弛，薄硅层变形，多孔硅层部分变形。

    LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON
    3.
    发明申请
    LOW DEFECT III-V SEMICONDUCTOR TEMPLATE ON POROUS SILICON 审中-公开

    公开(公告)号：US20190043956A1

    公开(公告)日：2019-02-07

    申请号：US16018304

    申请日：2018-06-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Dominic J. Schepis

    IPC: H01L29/16 ,  H01L21/02

    Abstract: A method of forming a semiconductor on a porous semiconductor structure. The method may include forming a stack, the stack includes (from bottom to top) a substrate, a base silicon layer, a thick silicon layer, and a thin silicon layer, where the thin silicon layer and the thick silicon layer are relaxed; converting the thick silicon layer into a porous silicon layer using a porousification process; and forming a III-V layer on the thin silicon layer, where the layer is relaxed, the thin silicon layer is strained, and the porous silicon layer is partially strained.

    SOI BASED FINFET WITH STRAINED SOURCE-DRAIN REGIONS
    5.
    发明申请
    SOI BASED FINFET WITH STRAINED SOURCE-DRAIN REGIONS 有权
    具有应变源 - 漏区的SOI基FINFET

    公开(公告)号：US20160190302A1

    公开(公告)日：2016-06-30

    申请号：US14585742

    申请日：2014-12-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

    IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

    CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

    Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

    Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

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