公开(公告)号：US10056306B2

公开(公告)日：2018-08-21

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US20180108535A1

公开(公告)日：2018-04-19

申请号：US15297848

申请日：2016-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy C. Krywanczyk ,  Patrick A. Raymond ,  John C. Hall ,  Damyon L. Corbin

IPC: H01L21/306 ,  H01L21/265 ,  H01L21/66

CPC classification number: H01L21/30604 ,  H01L21/26533 ,  H01L21/32137 ,  H01L21/3215 ,  H01L21/32155 ,  H01L22/26

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.

公开(公告)号：US10192748B2

公开(公告)日：2019-01-29

申请号：US15297848

申请日：2016-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Timothy C. Krywanczyk ,  Patrick A. Raymond ,  John C. Hall ,  Damyon L. Corbin

IPC: H01L21/302 ,  H01L21/306 ,  H01L21/265 ,  H01L21/66 ,  H01L21/3215 ,  H01L21/3213

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a method to control depth of etch in deep via etching and related structures. The method includes: forming an interface within the substrate between an etch control dopant and material of the substrate; etching a via within substrate; and terminating the etching of the via at the interface upon detection of the interface.

公开(公告)号：US20170229358A1

公开(公告)日：2017-08-10

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.