公开(公告)号：US20170229358A1

公开(公告)日：2017-08-10

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US10056306B2

公开(公告)日：2018-08-21

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US09577023B2

公开(公告)日：2017-02-21

申请号：US13909464

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Dinh Dang ,  David A. DeMuynck ,  Sarah A. McTaggart ,  Gary L. Milo ,  Melissa J. Roma ,  Jeffrey L. Thompson ,  Thomas W. Weeks

IPC: H01F5/00 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another.

Abstract translation: 一种包括在第一电介质层中形成第一金属线的方法，所述第一金属线包括与第二垂直侧相对的第一垂直侧; 以及在所述第一电介质层上方的第二电介质层中形成第二金属线，所述第二金属线包括与第四垂直侧相反的第三垂直侧，其中所述第一垂直侧从所述第三垂直侧横向偏移第一预定 距离，第二垂直侧从第四垂直侧横向偏移第二预定距离，其中第一金属线和第二金属线彼此直接接触。

公开(公告)号：US09484301B2

公开(公告)日：2016-11-01

申请号：US14718466

申请日：2015-05-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Max G. Levy ,  Gary L. Milo ,  Matthew D. Moon ,  Anthony C. Speranza ,  Timothy D. Sullivan ,  David C. Thomas ,  Steven S. Williams

IPC: H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76883 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.

公开(公告)号：US09435948B2

公开(公告)日：2016-09-06

申请号：US14304318

申请日：2014-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Robert K. Leidy ,  Mark D. Levy ,  Qizhi Liu ,  Gary L. Milo ,  Steven M. Shank

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

Abstract: Various embodiments include a silicon-based optical waveguide structure locally on a bulk silicon substrate, and systems and program products for forming such a structure by modifying an integrated circuit (IC) design structure. Embodiments include implementing processes of preparing manufacturing data for formation of the IC design structure in a computer-implemented IC formation system, wherein the preparing of the manufacturing data includes inserting instructions into the manufacturing data to convert an edge of the at least one shape from a crystallographic direction to a crystallographic direction.

Abstract translation: 各种实施例包括局部在体硅衬底上的硅基光波导结构，以及用于通过修改集成电路（IC）设计结构来形成这种结构的系统和程序产品。 实施例包括实现在计算机实现的IC形成系统中准备用于形成IC设计结构的制造数据的过程，其中制造数据的准备包括将指令插入到制造数据中以将至少一种形状的边缘从 <110>结晶方向到<100>晶体方向。