公开(公告)号：US09553061B1

公开(公告)日：2017-01-24

申请号：US14946208

申请日：2015-11-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Donald R. Letourneau ,  Patrick S. Spinney ,  Leah J. Bagley ,  John M. Sutton

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/311

CPC classification number: H01L24/06 ,  H01L21/311 ,  H01L22/32 ,  H01L22/34 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03618 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/06515 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/03831

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to wire bond pad structures and methods of manufacture. The structure includes: bond pads in an active region of a chip; test pad structures in a kerf region of the chip; and hardmask material in the kerf region between the test pad structures and the bond pads. The surfaces of the test pad structures and the bond pads are devoid of the hardmask material.

Abstract translation: 本公开涉及半导体结构，更具体地，涉及引线键合焊盘结构和制造方法。 该结构包括：芯片的有源区中的接合焊盘; 在芯片的切口区域中的测试焊盘结构; 以及在测试焊盘结构和接合焊盘之间的切口区域中的硬掩模材料。 测试焊盘结构和接合焊盘的表面没有硬掩模材料。

公开(公告)号：US20190139841A1

公开(公告)日：2019-05-09

申请号：US15804165

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Patrick S. Spinney ,  Jeffrey C. Stamm

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L21/78

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.

公开(公告)号：US10056306B2

公开(公告)日：2018-08-21

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  H01L23/544 ,  G01R31/28

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.

公开(公告)号：US10699973B2

公开(公告)日：2020-06-30

申请号：US15804165

申请日：2017-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Patrick S. Spinney ,  Jeffrey C. Stamm

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/66 ,  H01L21/78

Abstract: A test structure for semiconductor chips of a wafer, and the method of forming the same is included. The test structure may include a first portion disposed within a corner area of a first chip on the wafer, and at least another portion disposed within another corner of another chip on the wafer, wherein before dicing of the chips, the portions form the test structure. The test structure may include an electronic test structure or an optical test structure. The electronic test structure may include probe pads, each probe pad positioned across two or more corner areas of two or more chips. The corner areas including the test structures disposed therein may be removed from the chips during a dicing of the chips.

公开(公告)号：US20170229358A1

公开(公告)日：2017-08-10

申请号：US15015478

申请日：2016-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward C. Cooney, III ,  Gary L. Milo ,  Thomas W. Weeks ,  Patrick S. Spinney ,  John C. Hall ,  Brian P. Conchieri ,  Brett T. Cucci ,  Thomas C. Lee

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/544

CPC classification number: H01L22/32 ,  G01R31/2853 ,  G01R31/2884 ,  H01L22/34 ,  H01L23/544

Abstract: Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a first via disposed over the wire and in electrical contact with the wire. Each device includes a test pad electrically connected to the first via and a polysilicon resistor electrically connected to the wire. Each of the polysilicon resistors of the two or more devices are electrically tied together. A method for forming the interconnect structure to be used for testing is also provided.