公开(公告)号：US10735000B1

公开(公告)日：2020-08-04

申请号：US16720181

申请日：2019-12-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dzung T. Tran ,  Sushama Davar

IPC: H03K19/017 ,  H03K19/003

Abstract: A disclosed pre-driver includes multiple signal generation stages and a switching bias circuit with a first switch and a second switch. The first switch and primary inverters in each of the stages all receive the same input signal. When the input signal transitions, the first switch turns on the bias circuit to supply a bias voltage to each of the stages. However, the primary inverters do not concurrently turn on. Instead, due to the bias voltage and some additional circuitry within each stage, the primary inverters turn on in sequence and slowly, thereby ensuring that pre-driver signals generated and output by the different stages, respectively, transition in sequence and at a relatively slow rate. Once the last pre-driver signal transitions, the second switch turns off the switching bias circuit. Optionally, a selected one of multiple bias voltages could be used in order to tune delay and transition times.

公开(公告)号：US09547741B2

公开(公告)日：2017-01-17

申请号：US14518939

申请日：2014-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50 ,  H01L29/06 ,  H01L29/66

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/06 ,  H01L29/0661 ,  H01L29/6681

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计; 该设计包括第一功能单元和第二功能单元。 第一个功能单元放置在电路布局上。 确定第一单元是否包括电浮动的垂直边界。 响应于确定第一单元包括电浮动的垂直边界，填充单元被放置在电路布局上的垂直边界附近。 第二功能单元被放置成与填充单元相邻以在电路布局上形成连续的有效区域。

公开(公告)号：US09245087B1

公开(公告)日：2016-01-26

申请号：US14473986

申请日：2014-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L27/0207 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/78 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract translation: 本文公开的至少一种方法，装置和系统涉及在FinFET器件上进行功率降低处理。 提供了第一个设计。 第一设计包括处理掩模定义，FinFET器件，其包括由所述处理掩模表征的多个鳍片，以及与所述FinFET器件的操作相关的定时要求。 确定所述FinFET器件的所述操作的定时参数。 基于所述定时参数，确定所述FinFET器件的驱动能力是否高于维持所述定时要求所需的电平。 修改过程掩模以响应于所述确定所述驱动能力高于维持所述定时要求所需的水平的至少一个所述鳍片。

公开(公告)号：US10819110B2

公开(公告)日：2020-10-27

申请号：US15906475

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Manjunatha G. Prabhu ,  Alain F. Loiseau ,  Mahbub Rashed ,  Sushama Davar

IPC: H02H9/04 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

公开(公告)号：US10333497B1

公开(公告)日：2019-06-25

申请号：US15944813

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Mahbub Rashed ,  Sushama Davar ,  Navneet Jain

IPC: H03K3/011 ,  G06F13/10 ,  H03K5/24

Abstract: A calibration circuit is connected to an input/output driver, a voltage bias generator is connected to the calibration circuit and the input/output driver, and a temperature sensor is connected to the voltage bias generator. The calibration circuit and input/output driver each include a bank of resistors and corresponding switches. Bodies of the switches are connected to the voltage bias generator, and the switches are biased by a bias signal output from the voltage bias generator. The calibration circuit includes a comparator device connected to the switches and to a reference resistor. Activation and deactivation of selected ones of the switches is made to match the reference resistor. Also, the voltage bias generator adjusts the bias signal when a temperature change is sensed by the temperature sensor. Thus, the switches change current flow as the bias signal changes, without changing which of the switches are activated or deactivated.

公开(公告)号：US20160099239A1

公开(公告)日：2016-04-07

申请号：US14965639

申请日：2015-12-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/0207 ,  G06F17/5031 ,  G06F17/5081 ,  G06F2217/78 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein involves performing power reduction process on a FinFET device. A first design is provided. The first design comprises a process mask definition, a FinFET device that comprises a plurality of fins characterized by said process mask, and a timing requirement relating to an operation of said FinFET device. A timing parameter of said operation of said FinFET device is determined. Based upon said timing parameter, a determination is made as to whether a drive capability of said FinFET device is above a level required to maintain said timing requirement. The process mask is modified for reducing at least one of said fins in response to said determining that said drive capability is above said level required to maintain said timing requirement.

Abstract translation: 本文公开的至少一种方法，装置和系统涉及在FinFET器件上进行功率降低处理。 提供了第一个设计。 第一设计包括处理掩模定义，FinFET器件，其包括由所述处理掩模表征的多个鳍片，以及与所述FinFET器件的操作相关的定时要求。 确定所述FinFET器件的所述操作的定时参数。 基于所述定时参数，确定所述FinFET器件的驱动能力是否高于维持所述定时要求所需的电平。 修改过程掩模以响应于所述确定所述驱动能力高于维持所述定时要求所需的水平的至少一个所述鳍片。

公开(公告)号：US20160110489A1

公开(公告)日：2016-04-21

申请号：US14518939

申请日：2014-10-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Uwe Paul Schroeder ,  Sushama Davar

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/06 ,  H01L29/0661 ,  H01L29/6681

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计; 该设计包括第一功能单元和第二功能单元。 第一个功能单元放置在电路布局上。 确定第一单元是否包括电浮动的垂直边界。 响应于确定第一单元包括电浮动的垂直边界，填充单元被放置在电路布局上的垂直边界附近。 第二功能单元被放置成与填充单元相邻以在电路布局上形成连续的有效区域。