公开(公告)号：US20190229207A1

公开(公告)日：2019-07-25

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/768 ,  H01L21/761

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US10361293B1

公开(公告)日：2019-07-23

申请号：US15878478

申请日：2018-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Tsung-Che Tsai ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Souvick Mitra ,  You Li ,  Mickey H. Yu

IPC: H01L29/74 ,  H01L29/868 ,  H01L23/535 ,  H01L21/761 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L27/02

Abstract: Disclosed is an integrated circuit (IC) structure that incorporates a string of vertical devices. Embodiments of the IC structure include a string of two or more vertical diodes. Other embodiments include a vertical diode/silicon-controlled rectifier (SCR) string and, more particularly, a diode-triggered silicon-controlled rectifier (VDTSCR). In any case, each embodiment of the IC structure includes an N-well in a substrate and, within that N-well, a P-doped region and an N-doped region that abuts the P-doped region. The P-doped region can be anode of a vertical diode and can be electrically connected to the N-doped region (e.g., by a local interconnect or by contacts and metal wiring) such that the vertical diode is electrically connected to another vertical device (e.g., another vertical diode or a SCR with vertically-oriented features). Also disclosed is a manufacturing method that can be integrated with methods of manufacturing vertical field effect transistors (VFETs).

公开(公告)号：US10819110B2

公开(公告)日：2020-10-27

申请号：US15906475

申请日：2018-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anil Kumar ,  Manjunatha G. Prabhu ,  Alain F. Loiseau ,  Mahbub Rashed ,  Sushama Davar

IPC: H02H9/04 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection circuits and methods of use and manufacture. The structure includes: an electrostatic discharge (ESD) clamp which receives an input signal from a trigger circuit; and a voltage node connecting to a back gate of the ESD clamp, the voltage node providing a voltage to the ESD clamp during an electrostatic discharge (ESD) event.

公开(公告)号：US10541236B2

公开(公告)日：2020-01-21

申请号：US16018549

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Souvick Mitra ,  Mickey Yu ,  Alain F. Loiseau ,  You Li ,  Robert J. Gauthier, Jr. ,  Tsung-Che Tsai

IPC: H01L27/02 ,  H01L23/60 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge structures with reduced capacitance and methods of manufacture. The structure includes: a plurality of fin structures provided in at least one N+ type region and at least one P+ region; and a plurality of gate structures disposed over the plurality of fin structures and within the at least one N+ type region and one P+ region, the plurality of gate structures being separated in a lengthwise direction between the at least one N+ type region and the least one P+ region.

公开(公告)号：US20190214381A1

公开(公告)日：2019-07-11

申请号：US15866999

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ahmed Y. GINAWI ,  Andreas D. Stricker ,  Alain F. Loiseau ,  Ephrem G. Gebreselasie ,  Joseph M. Lukaitis ,  Richard A. Poro, III

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0266 ,  H01L27/0292 ,  H01L27/0296 ,  H02H9/044 ,  H02H9/046

Abstract: The present disclosure relates to an electrostatic discharge (ESD) clamp and, more particularly, to an ESD clamp with reduced off-state power consumption. The structure includes: one or more inverters connected to a timing circuit; a first transistor receiving an output signal from a last of the one or more inverters and an output signal from the timing circuit; a second transistor with its gate connected to the first transistor, in series; and a voltage node providing a separate voltage to a gate of the second transistor.

公开(公告)号：US09940986B2

公开(公告)日：2018-04-10

申请号：US14971644

申请日：2015-12-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Alain F. Loiseau ,  Joseph M. Lukaitis ,  Ephrem G. Gebreselasie ,  Richard A. Poro ,  Andreas D. Stricker ,  Ahmed Y. Ginawi

IPC: H02H9/04 ,  G11C7/24 ,  H01L23/525 ,  H01L27/02 ,  H01L27/06 ,  H01L27/112 ,  G11C5/00 ,  G11C17/16

CPC classification number: G11C7/24 ,  G11C5/005 ,  G11C17/16 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0617 ,  H01L27/11206

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The structure includes an electrostatic discharge (ESD) protection structure operatively coupled to an eFuse, which is structured to prevent unintentional programming of the eFuse due to an ESD event originating at a source.