公开(公告)号：US09881669B1

公开(公告)日：2018-01-30

申请号：US15446091

申请日：2017-03-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Vinay Bhatsoori

IPC: G11C11/34 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/222 ,  G11C8/08 ,  G11C11/418

Abstract: Disclosed is a wordline driver with an integrated voltage level shift function. This wordline driver receives a decoder output signal from a wordline address decoder operating at first voltage level. Based on the decoder output signal, it generates and outputs a wordline driving signal, which selectively activates or deactivates a selected wordline. To ensure that the selected wordline, when activated, is at a second voltage level that is higher than the first, the wordline driver uses a combination of clock signals received from multiple timing control blocks operating at the first voltage level and multiple logic gates operating the second voltage level. To ensure that this wordline driving signal remains low during power up when fluctuations occur due to the different voltage levels and, specifically, to ensure that the wordline driving signal only switches to high when it will be stable, the wordline driver can include a reset control block.

公开(公告)号：US09390769B1

公开(公告)日：2016-07-12

申请号：US14922323

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vinay Bhatsoori ,  George M. Braceras ,  Venkatraghavan Bringivijayaraghavan

IPC: G11C7/00 ,  G11C7/06 ,  H03K3/037 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/037

Abstract: Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.

Abstract translation: 多路复用锁存器包括具有第一数据输入，第二数据输入，选择输入和多路复用器输出的多路复用器。 第一锁存器具有第一锁存器时钟输入和第一锁存器输出。 第二锁存器具有第二锁存器时钟输入和第二锁存器输出。 第一锁存器输出连接到多路复用器的第一数据输入端，第二锁存器输出端连接到多路复用器的第二数据输入端。 反馈回路将多路复用器输出连接到第一锁存时钟输入和第二锁存时钟输入。 当多路复用器接收到选择信号时，反馈环路将多路复用器的输出反馈给锁存器，以保持现有的锁存器输出，直到时钟信号转换为止，以避免在选择信号和时钟信号为 不同步