公开(公告)号：US10522217B1

公开(公告)日：2019-12-31

申请号：US16057857

申请日：2018-08-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  Eswararao Potladhurthi ,  George M. Braceras

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.

公开(公告)号：US09570156B1

公开(公告)日：2017-02-14

申请号：US14832127

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George M. Braceras ,  Venkatraghavan Bringivijayaraghavan ,  Sheikh S. Chishti

IPC: G11C11/00 ,  G11C11/419 ,  G11C5/14 ,  G11C11/412 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.

Abstract translation: 提供了一种为静态随机存取存储器（SRAM）阵列提供写入辅助的方法。 电路包括连接到SRAM阵列中的单元的控制电路。 所述控制电路被配置为：在对所述单元的写入操作期间，将第一电压施加到所述单元的第一下拉晶体管; 并且在写入操作期间将不同于第一电压的第二电压施加到单元的第二下拉晶体管。

公开(公告)号：US09390769B1

公开(公告)日：2016-07-12

申请号：US14922323

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vinay Bhatsoori ,  George M. Braceras ,  Venkatraghavan Bringivijayaraghavan

IPC: G11C7/00 ,  G11C7/06 ,  H03K3/037 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C7/1051 ,  G11C7/106 ,  H03K3/037

Abstract: Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.

Abstract translation: 多路复用锁存器包括具有第一数据输入，第二数据输入，选择输入和多路复用器输出的多路复用器。 第一锁存器具有第一锁存器时钟输入和第一锁存器输出。 第二锁存器具有第二锁存器时钟输入和第二锁存器输出。 第一锁存器输出连接到多路复用器的第一数据输入端，第二锁存器输出端连接到多路复用器的第二数据输入端。 反馈回路将多路复用器输出连接到第一锁存时钟输入和第二锁存时钟输入。 当多路复用器接收到选择信号时，反馈环路将多路复用器的输出反馈给锁存器，以保持现有的锁存器输出，直到时钟信号转换为止，以避免在选择信号和时钟信号为 不同步

公开(公告)号：US10510384B2

公开(公告)日：2019-12-17

申请号：US15814969

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  George M. Braceras

IPC: G11C11/419 ,  G11C7/12 ,  G11C11/4074 ,  H04L5/22 ,  G11C11/406 ,  G11C11/56

Abstract: The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.

公开(公告)号：US09721628B1

公开(公告)日：2017-08-01

申请号：US15266261

申请日：2016-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Venkatraghavan Bringivijayaraghavan ,  George M. Braceras

IPC: G11C7/08 ,  G11C7/22 ,  G11C7/06 ,  G11C8/10 ,  G11C7/10 ,  G11C8/08

CPC classification number: G11C7/22 ,  G11C7/08 ,  G11C7/1012 ,  G11C8/08 ,  G11C8/10 ,  G11C11/408 ,  G11C11/418 ,  G11C11/419 ,  G11C2207/005

Abstract: Data paths are provided to a memory array. The data paths include switches for selectively aligning the data paths to different multiplexors for reading or writing to the memory array. Read data lines are steered to selected sense amplifiers based on the decode address, using the switches. Write data lines are steered to selected write drivers based on the decode address, using the switches.

公开(公告)号：US20170053694A1

公开(公告)日：2017-02-23

申请号：US14832127

申请日：2015-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George M. Braceras ,  Venkatraghavan Bringivijayaraghavan ,  Sheikh S. Chishti

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/412 ,  G11C11/413

Abstract: Approaches for providing write-assist for a Static Random Access Memory (SRAM) array are provided. A circuit includes a control circuit connected to a cell in a SRAM array. The control circuit is configured to: apply a first voltage to a first pull down transistor of the cell during a write operation to the cell; and apply a second voltage, different than the first voltage, to a second pull down transistor of the cell during the write operation.

Abstract translation: 提供了一种为静态随机存取存储器（SRAM）阵列提供写入辅助的方法。 电路包括连接到SRAM阵列中的单元的控制电路。 所述控制电路被配置为：在对所述单元的写入操作期间，将第一电压施加到所述单元的第一下拉晶体管; 并且在写入操作期间将不同于第一电压的第二电压施加到单元的第二下拉晶体管。

公开(公告)号：US09437282B1

公开(公告)日：2016-09-06

申请号：US14819784

申请日：2015-08-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George M. Braceras ,  Venkatraghavan Bringivijayaraghavan ,  Krishnan S. Rengarajan

IPC: G11C7/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/065

Abstract: A sense amplifier device for sensing a differential signal produced by a memory cell includes a first n-type metal-oxide-semiconductor field-effect transistor (NMOS) stack having multiple NMOS devices sharing a gate connection connected to a complementary data line; and a second NMOS stack having multiple NMOS devices sharing a gate connection connected to a true data line. At least one of the devices in the first stack has higher gate-to-source and drain-to-source voltages than a gate-to-source and drain-to-source voltages of at least one device in the second stack when the voltage of the complementary data line is higher than the true data line. At least one of the devices in the second stack has a higher gate-to-source and drain-to-source voltages than the gate-to-source and drain-to-source voltages of at least one device in the first stack when the voltage of the true data line is higher than the complementary data line.

Abstract translation: 用于感测由存储单元产生的差分信号的读出放大器装置包括：具有多个NMOS器件的第一n型金属氧化物半导体场效应晶体管（NMOS）堆叠，共享连接到互补数据线的栅极连接; 以及具有共享连接到真实数据线的栅极连接的多个NMOS器件的第二NMOS堆叠。 当第一堆叠中的至少一个器件具有比第二堆叠中的至少一个器件的栅极至源极和漏极至源极电压更高的栅极至源极和漏极至源极电压， 的补充数据线高于真实数据线。 第二堆叠中的至少一个器件具有比第一堆叠中的至少一个器件的栅极至源极和漏极至源极电压更高的栅极至源极和漏极至源极电压， 真实数据线的电压高于补充数据线。