公开(公告)号：US10658388B2

公开(公告)日：2020-05-19

申请号：US16414203

申请日：2019-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Pawlak

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/786 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/822 ,  H01L27/06

Abstract: A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.

公开(公告)号：US10340290B2

公开(公告)日：2019-07-02

申请号：US15706048

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Pawlak

IPC: H01L27/01 ,  H01L27/12 ,  H01L29/06 ,  H01L21/84 ,  H01L21/822 ,  H01L27/06

Abstract: A semiconductor device includes at least two stacked SOI levels or configurations, each of which may include transistor elements formed on the basis of a given technology node. At least the uppermost device level may include a back bias mechanism for providing superior controllability of the respective transistor elements. In some illustrative embodiments, at least two of the stacked SOI configurations may have implemented therein a back bias mechanism, wherein an appropriate contact regime is provided so as to connect to the respective conductive regions or layers below the corresponding buried insulating layers for each stacked device level. Consequently, increased lateral packing density may be accomplished on the basis of a given technology node.

公开(公告)号：US10090227B1

公开(公告)日：2018-10-02

申请号：US15648602

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Pawlak ,  Luke England

IPC: H01L23/48 ,  H01L27/12 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/56

Abstract: In one aspect, the present disclosure provides a semiconductor device structure with a silicon-on-insulator (SOI) substrate composed of an active layer, a substrate and a buried insulating layer which is positioned on an upper surface of the substrate and below a lower surface of the active layer. At least one gate electrode having a channel region below is positioned above an upper surface of the active layer and at least one vertical connection element extends between the upper surface of the substrate and an opposite lower surface of the substrate below the at least one gate electrode. The at least one vertical connection element serves for back-biasing FETs with back-bias contacts at the rear side of the wafer.

公开(公告)号：US20190280010A1

公开(公告)日：2019-09-12

申请号：US16414203

申请日：2019-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Pawlak

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/84

Abstract: A method includes forming a first circuit element in and above a first semiconductor layer, the first semiconductor layer being formed on a first buried insulating layer, forming drain and source regions of the first circuit element at least partially in the first semiconductor layer, and forming a layer stack above the first circuit element, the layer stack including a conductive layer, a second buried insulating layer formed above the conductive layer, and a second semiconductor layer formed above the second buried insulating layer, wherein the conductive layer is electrically isolated from the drain and source regions.

公开(公告)号：US09698262B2

公开(公告)日：2017-07-04

申请号：US15072130

申请日：2016-03-16

Applicant: IMEC VZW ,  GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Pawlak ,  Geert Eneman

IPC: H01L29/74 ,  H01L29/80 ,  H01L29/94 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/76 ,  H01L21/765 ,  H01L29/0607 ,  H01L29/0657 ,  H01L29/1083 ,  H01L29/42356

Abstract: A vertical FinFET semiconductor device and a method of forming the same are disclosed. In one aspect, the semiconductor device includes a current-blocking structure formed over a semiconductor structure and a semiconductor fin formed on the current-blocking structure. The current blocking structure includes a first layer of a first conductive type, a layer of a second conductive type over the first layer, and a second layer of the first conductive type over the layer of the second conductive type. The semiconductor fin has a doped bottom portion contacting the current-blocking structure, a doped top portion formed vertically opposite to the doped bottom portion and a channel portion vertically interposed between the doped bottom portion and the doped top portion.

公开(公告)号：US20190088680A1

公开(公告)日：2019-03-21

申请号：US15706048

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Pawlak

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823475 ,  H01L21/84 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/78648

Abstract: A semiconductor device includes at least two stacked SOI levels or configurations, each of which may include transistor elements formed on the basis of a given technology node. At least the uppermost device level may include a back bias mechanism for providing superior controllability of the respective transistor elements. In some illustrative embodiments, at least two of the stacked SOI configurations may have implemented therein a back bias mechanism, wherein an appropriate contact regime is provided so as to connect to the respective conductive regions or layers below the corresponding buried insulating layers for each stacked device level. Consequently, increased lateral packing density may be accomplished on the basis of a given technology node.