公开(公告)号：US20190051757A1

公开(公告)日：2019-02-14

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

公开(公告)号：US10128334B1

公开(公告)日：2018-11-13

申请号：US15672336

申请日：2017-08-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie Bourjot ,  Ruilong Xie

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/72 ,  H01L29/66

Abstract: A method is disclosed wherein a gate, having a gate cap and a sacrificial gate sidewall spacer, is formed adjacent to channel region(s) of a transistor and metal plugs, having plug caps, are formed on source/drain regions. The sacrificial gate sidewall spacer is selectively etched, creating a cavity that exposes sidewalls of the gate and gate cap. Optionally, the sidewalls of the gate cap are etched back to widen the upper portion of the cavity. A dielectric spacer layer is deposited to form an air-gap gate sidewall spacer within the cavity. Since different materials are used for the plug caps, gate cap and dielectric spacer layer, a subsequently formed gate contact opening will be self-aligned to the gate. Thus, a gate contact can be formed over an active region (or close thereto) without risk of gate contact-to-metal plug shorting. A structure formed according to the method is also disclosed.

公开(公告)号：US10797138B2

公开(公告)日：2020-10-06

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/00 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10236296B1

公开(公告)日：2019-03-19

申请号：US15861097

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot ,  Bipul C. Paul

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/528 ,  H01L23/535

Abstract: An IC product disclosed herein includes a first merged doped source/drain (MDSD) region having an upper surface, a first side surface and a second side surface that intersect one another at a corner of the first merged doped source/drain region, a second MDSD region and a contact trench in an isolation structure positioned between the first and second MDSD regions. The product also includes a conductive gate structure positioned above at least the second MDSD region and a cross-coupled contact structure that comprises a first portion positioned within the contact trench laterally adjacent to and conductively coupled to at least one of the first side surface and the second side surface, and a second portion that is positioned above and conductively coupled to the upper surface of the MDSD region, wherein the cross-coupled contact structure is conductively coupled to the conductive gate structure.

公开(公告)号：US10388747B1

公开(公告)日：2019-08-20

申请号：US15938510

申请日：2018-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Emilie Bourjot ,  Laertis Economikos

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L23/535 ,  H01L21/764

Abstract: One illustrative integrated circuit product disclosed herein includes a transistor device comprising a T-shaped gate structure positioned above an active region defined in a semiconducting substrate, the T-shaped portion of the gate structure comprising a relatively wider upper portion and a relatively narrower lower portion, and first and second conductive source/drain structures positioned adjacent opposite sidewalls of the T-shaped gate structure. In this example, the product also includes first and second air gaps positioned adjacent opposite sidewall of the T-shaped gate structure, wherein each of the air gaps is positioned between at least the lower portion of one of the sidewalls of the T-shaped gate structure and the adjacent conductive source/drain structure.

公开(公告)号：US20190206878A1

公开(公告)日：2019-07-04

申请号：US15861161

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/41741 ,  H01L29/7827

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

公开(公告)号：US20190312116A1

公开(公告)日：2019-10-10

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10381354B2

公开(公告)日：2019-08-13

申请号：US15861161

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

公开(公告)号：US10230000B2

公开(公告)日：2019-03-12

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.