公开(公告)号：US10170544B2

公开(公告)日：2019-01-01

申请号：US15833285

申请日：2017-12-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

Abstract: An integrated circuit product includes a FinFET device, a device isolation region that is positioned around a perimeter of the FinFET device, and an isolation protection layer that is positioned above the device isolation region. The FinFET device includes at least one fin, a gate structure, and a sidewall spacer, the device isolation region includes a first insulating material, and the isolation protection layer includes a material that is different from the first insulating material. A first portion of the isolation protection layer is positioned under a portion of the gate structure and under a portion of the sidewall spacer, wherein a second portion of the isolation protection layer is not positioned under the gate structure and is not positioned under the sidewall spacer, the first portion of the isolation protection layer having a thickness that is greater than a thickness of the second portion.

公开(公告)号：US10109714B2

公开(公告)日：2018-10-23

申请号：US15694109

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L21/82 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US20180006111A1

公开(公告)日：2018-01-04

申请号：US15197944

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Christopher M. Prindle ,  Min Gyu Sung ,  Tek Po Rinus Lee

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of trenches in a semiconductor substrate so as to define a plurality of fins, forming a recessed layer of insulating material comprising a first insulating material in the trenches, wherein a portion of each of the plurality of fins is exposed above an upper surface of the recessed layer of insulating material, and masking a first portion of a first fin and performing at least one first etching process to remove at least a portion of an unmasked second fin. In this example, the method further includes forming a device isolation region for the FinFET device that comprises a second insulating material and forming an isolation protection layer above the device isolation region.

公开(公告)号：US20190051757A1

公开(公告)日：2019-02-14

申请号：US15671605

申请日：2017-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Tek Po Rinus Lee ,  Ruilong Xie ,  Hui Zang

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: Methods and structures that include a vertical-transport field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A second source/drain region is spaced vertically along the semiconductor fin from the first source/drain region. A gate stack is arranged between the second source/drain region and the first source/drain region. A spacer is formed adjacent to a sidewall of the second source/drain region. A first contact is connected with a top surface of the second source/drain region, a second contact is connected with a top surface of the first source/drain region, and a third contact is connected with a top surface of the gate stack. The spacer is arranged between the second source/drain region and the second contact or between the second source/drain region and the third contact.

公开(公告)号：US10103238B1

公开(公告)日：2018-10-16

申请号：US15652890

申请日：2017-07-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee ,  Haigou Huang ,  Ruilong Xie ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768 ,  H01L29/06 ,  H01L21/311 ,  H01L29/786 ,  H01L21/02

Abstract: Methods for forming a structure for a nanosheet field-effect transistor. A body feature is formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial layers that are alternatingly arranged with the nanosheet channel layers. The body feature is located on a second sacrificial layer. The first sacrificial layers are recessed relative to the nanosheet channel layers to form a plurality of first cavities indented into a sidewall of the body feature. A plurality of dielectric spacers are formed that fill the first cavities. After forming the dielectric spacers, the second sacrificial layer is removed with an etching process to define a second cavity that extends completely beneath the body feature. A dielectric layer is formed in the second cavity.

公开(公告)号：US09831317B1

公开(公告)日：2017-11-28

申请号：US15447639

申请日：2017-03-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L21/285 ,  H01L21/311

CPC classification number: H01L29/41741 ,  H01L21/28556 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US10276683B2

公开(公告)日：2019-04-30

申请号：US15718958

申请日：2017-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Jinping Liu ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/40 ,  H01L29/47 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/285 ,  H01L27/092 ,  H01L21/8238

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include a semiconductor substrate having an n-FET region and a p-FET region each having source/drain regions; a titanium silicon (Ti—Si) intermix phase Ti liner on an upper surface of the n-FET region source/drain regions; and titanium silicide (TiSi) forming an upper surface of the p-FET region source/drain regions.

公开(公告)号：US20180254327A1

公开(公告)日：2018-09-06

申请号：US15694109

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Tek Po Rinus Lee

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/10 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L29/41741 ,  H01L21/28556 ,  H01L21/31116 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: Structures including a vertical field-effect transistor and fabrication methods for a structure including a vertical field-effect transistor. A vertical field-effect transistor includes a source/drain region located in a section of a semiconductor layer, a first semiconductor fin projecting from the source/drain region, a second semiconductor fin projecting from the source/drain region, and a gate electrode on the section of the semiconductor layer and coupled with the first semiconductor fin and with the second semiconductor fin. The structure further includes a contact located in a trench defined in the section of the semiconductor layer between the first semiconductor fin and the second semiconductor fin. The contact is coupled with the source/drain region of the vertical field-effect transistor.

公开(公告)号：US09812543B2

公开(公告)日：2017-11-07

申请号：US15060761

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Jinping Liu ,  Ruilong Xie

IPC: H01L21/266 ,  H01L29/47 ,  H01L29/40 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.