公开(公告)号：US20210043733A1

公开(公告)日：2021-02-11

申请号：US16535338

申请日：2019-08-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lars Mueller-Meskamp ,  Luca Pirro

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/423

Abstract: One illustrative device disclosed herein includes a gate structure positioned above an active semiconductor layer of an SOI substrate and a counter-doped back-gate region positioned in the doped base semiconductor substrate of the SOI substrate. In this particular embodiment, the device also includes a counter-doped back-gate contact region positioned in the base semiconductor substrate, wherein the counter-doped back-gate region and the counter-doped back-gate contact region are doped with a dopant type that is opposite the dopant type in the base semiconductor substrate. In this illustrative example, the counter-doped back-gate region and the counter-doped back-gate contact region are laterally separated from one another by a portion of the doped base semiconductor substrate. The device also includes a conductive back-gate contact structure that is conductively coupled to the counter-doped back-gate contact region.

公开(公告)号：US20190109192A1

公开(公告)日：2019-04-11

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US10388514B2

公开(公告)日：2019-08-20

申请号：US15729815

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lars Mueller-Meskamp ,  Stefan Duenkel

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L21/265 ,  H01L21/223 ,  H01L29/06 ,  H01L29/66

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

公开(公告)号：US20190108998A1

公开(公告)日：2019-04-11

申请号：US15729815

申请日：2017-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lars Mueller-Meskamp ,  Stefan Duenkel

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/78 ,  H01L21/265 ,  H01L21/223 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/02299 ,  H01L21/02172 ,  H01L21/02181 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/76267 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66477 ,  H01L29/78391 ,  H01L29/7841

Abstract: In semiconductor devices, high-k dielectric materials may be formed on the basis of engineered surface conditions, thereby contributing to superior uniformity of the resulting characteristics. In some illustrative embodiments, the dielectric material may be stabilized in a ferroelectric phase, wherein the previous surface modulation, which, in the illustrative embodiments may include the introduction of respective species, such as dopant species, thereby contributing to uniform ferroelectric characteristics. In some illustrative embodiments, the process strategy may be applied to a buried insulating layer of an SOI substrate.

公开(公告)号：US10580863B2

公开(公告)日：2020-03-03

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L27/088 ,  H01L21/336 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L21/225 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.